MC68HC908RF2 Datasheet, PDF (172/254 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Low-Voltage Inhibit (LVI)
12.5 LVI Status Register
The LVI status register flags V_DD voltages below the V_LVR and V_LVS
levels.
Address: $FE0F
Bit 7
6
5
4
3
2
1
Bit 0
Read: LVIOUT
0
LOWV
0
0
0
0
0
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 12-2. LVI Status Register (LVISR)
LVIOUT — LVI Output Bit
The read-only flag becomes set when the V_DD voltage falls below the
V_LVR voltage for 32 to 40 CGMXCLK cycles. Reset clears the LVIOUT
bit.
LOWV— LVI Low Indicator Bit
This read-only flag becomes set when the LVI is detecting V_DD
voltage below the V_LVS threshold.
12.6 LVI Interrupts
The LVI module does not generate CPU interrupt requests.
12.7 Low-Power Modes
The STOP and WAIT instructions put the MCU in low power-
consumption standby modes.
Advance Information
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Low-Voltage Inhibit (LVI)
MC68HC908RF2 — Rev. 1
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