MC68HC908RF2 Datasheet, PDF (133/254 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Internal Clock Generator Module (ICG)
Usage Notes
The equations for t₁₅, t₅, and t_tot are dependent on the actual initial and
final clock periods t₁ and t₂, not the nominal. This means the variability
in the ICLK frequency due to process, temperature, and voltage must be
considered. Additionally, other process factors and noise can affect the
actual tolerances of the points at which the filter changes modes. This
means a worst case adjustment of up to 35 percent (ICLK clock period
tolerance plus 10 percent) must be added. This adjustment can be
reduced with trimming. Table 8-4 shows some typical values for settling
time.
Table 8-4. Typical Settling Time Examples
t₁
1/ (6.45 MHz)
1/ (25.8 MHz)
1/ (25.8 MHz)
1/ (307.2 kHz)
t₂
1/ (25.8 MHz)
1/ (6.45 MHz)
1/ (307.2 kHz)
1/ (25.8 MHz)
N
t₁₅
84 430 µs
21 107 µs
1
141 µs
84 11.9 ms
t₅
535 µs
212 µs
246 µs
12.0 ms
t_tot
850 µs
525 µs
560 µs
12.3 ms
8.5.7 Improving Settling Time
The settling time of the internal clock generator can be vastly improved
if an external clock source can be used during the settling time. When
the internal clock generator is disabled (ICGON is low), the DDIV[3:0]
and DSTG[7:0] bits can be written. Then, when the internal clock
generator is re-enabled, the clock period will automatically start at the
point written in the DDIV and DSTG bits.
Since a change in the DDIV and DSTG bits only cause a change in the
clock period relative to the starting point, the starting point must first be
captured. The initial clock period can be expressed as in the next
example, where t_X is a process, temperature, and voltage dependent
constant and DDIV1 and DSTG1 are the values of DDIV and DSTG
when operating at t₁.
t1 = tX ⋅ 2DDIV1 ⋅ DSTG1
MC68HC908RF2 — Rev. 1
MOTOROLA
Internal Clock Generator Module (ICG)
Advance Information
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