MC68HC908RF2 Datasheet, PDF (146/254 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Internal Clock Generator Module (ICG)
8.8.5 ICG DCO Stage Register
Address: $003A
Bit 7
6
5
4
3
2
1
Read:
DSTG7
Write:
DSTG6
DSTG5
DSTG4
DSTG3
DSTG2
DSTG1
Reset:
Unaffected by reset
Figure 8-15. ICG DCO Stage Register (ICGDSR)
Bit 0
DSTG0
DSTG7–DSTG0 — ICG DCO Stage Control Bits
These bits indicate the number of stages DSTG (above the minimum)
in the digitally controlled oscillator. The total number of stages is
approximately equal to $1FF, so changing DSTG from $00 to $FF will
approximately double the period. Incrementing DSTG will increase
the period (decrease the frequency) by 0.202 percent to 0.368
percent (decrementing has the opposite effect). DSTG cannot be
written when ICGON is set to prevent inadvertent frequency shifting.
When ICGON is set, DSTG is controlled by the digital loop filter. Since
the DCO is active during reset, reset has no effect on DSTG and the
value may vary.
Advance Information
146
Internal Clock Generator Module (ICG)
MC68HC908RF2 — Rev. 1
MOTOROLA