MC68HC908RF2 Datasheet, PDF (132/254 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Internal Clock Generator Module (ICG)
This series can be expressed as (2^x–1)*44*N*t_ICLKFAST, where x is the
number of times the speed needs doubled or halved. Since 2^x happens
to be equal to t_ICLKSLOW/t_ICLKFAST, the equation reduces to
44*N*(t_ICLKSLOW-t_ICLKFAST). Note that increasing speed takes much
longer than decreasing speed since N is higher. This can be expressed
in terms of the initial clock period (t₁) minus the final clock period (t₂) as
such:
t15 = abs[44N(t1 – t2)]
8.5.6.2 Settling to Within 5 Percent
Once the clock period is within 15 percent of the desired clock period,
the filter starts making smaller adjustments. When between 15 percent
and 5 percent error, each correction will adjust the clock period between
1.61 percent and 2.94 percent. In this mode, a maximum of eight
corrections will be required to get to less than 5 percent error. Since the
clock period is relatively close to desired, each correction takes
approximately the same period of time, or 4*t_IBASE. At this point, the
internal clock stable bit (ICGS) will be set and the clock frequency is
usable, although the error will be as high as 5 percent. The total time to
this point is:
t5 = abs[44N(t1 – t2)] + 32tIBASE
8.5.6.3 Total Settling Time
Once the clock period is within 5 percent of the desired clock period, the
filter starts making minimum adjustments. In this mode, each correction
will adjust the frequency between 0.202 percent and 0.368 percent. A
maximum of 24 corrections will be required to get to the minimum error.
Each correction takes approximately the same period of time or 4*t_IBASE.
Added to the corrections for 15 percent to 5 percent, this makes 32
corrections (128*t_IBASE) to get from 15 percent to the minimum error.
The total time to the minimum error is:
ttot = abs[44N(t1 – t2)] + 128tIBASE
Advance Information
132
Internal Clock Generator Module (ICG)
MC68HC908RF2 — Rev. 1
MOTOROLA