MC68HC908RF2 Datasheet, PDF (129/254 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Internal Clock Generator Module (ICG)
Usage Notes
the ring oscillator’s output is divided by 1. Incrementing DDIV by 1 will
double the period; decrementing DDIV will halve the period. The DLF
cannot directly increment or decrement DDIV; DDIV is only incremented
or decremented when an addition or subtraction to DSTG carries or
borrows.
8.5.4.3 Variable-Delay Ring Oscillator
The variable-delay ring oscillator’s period is adjustable from 17 to 31
stage delays, in increments of two, based on the upper three DCO stage
control bits (DSTG[7:5]). A DSTG[7:5] of %000 corresponds to 17 stage
delays; DSTG[7:5] of %111 corresponds to 31 stage delays. Adjusting
the DSTG[5] bit has a 6.45 percent to 11.8 percent effect on the output
frequency. This also corresponds to the size correction made when the
frequency error is greater than ±15 percent. The value of the binary
weighted divider does not affect the relative change in output clock
period for a given change in DSTG[7:5].
8.5.4.4 Ring Oscillator Fine-Adjust Circuit
The ring oscillator fine-adjust circuit causes the ring oscillator to
effectively operate at non-integer numbers of stage delays by operating
at two different points for a variable number of cycles specified by the
lower five DCO stage control bits (DSTG[4:0]). For example, when
DSTG[7:5] is %011, the ring oscillator nominally operates at 23 stage
delays. When DSTG[4:0] is %00000, the ring will always operate at 23
stage delays. When DSTG[4:0] is %00001, the ring will operate at 25
stage delays for one of 32 cycles and at 23 stage delays for 31 of 32
cycles. Likewise, when DSTG[4:0] is %11111, the ring operates at 25
stage delays for 31 of 32 cycles and at 23 stage delays for one of 32
cycles. When DSTG[7:5] is %111, similar results are achieved by
including a variable divide-by-two, so the ring operates at 31 stages for
some cycles and at 17 stage delays, with a divide-by-two for an effective
34 stage delays, for the remainder of the cycles. Adjusting the DSTG[0]
bit has a 0.202 percent to 0.368 percent effect on the output clock period.
This corresponds to the minimum size correction made by the DLF, and
the inherent, long-term quantization error in the output frequency.
MC68HC908RF2 — Rev. 1
MOTOROLA
Internal Clock Generator Module (ICG)
Advance Information
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