PIC18LF252-ISP Datasheet, PDF (94/332 Pages) Microchip Technology – High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D

PIC18FXX2
TABLE 9-3: PORTB FUNCTIONS
Name
Bit#
Buffer
Function
RB0/INT0
RB1/INT1
RB2/INT2
bit0 TTL/ST⁽¹⁾ Input/output pin or external interrupt input0.
Internal software programmable weak pull-up.
bit1 TTL/ST⁽¹⁾ Input/output pin or external interrupt input1.
Internal software programmable weak pull-up.
bit2 TTL/ST⁽¹⁾ Input/output pin or external interrupt input2.
Internal software programmable weak pull-up.
RB3/CCP2⁽³⁾
bit3 TTL/ST⁽⁴⁾ Input/output pin or Capture2 input/Compare2 output/PWM output when
CCP2MX configuration bit is enabled.
Internal software programmable weak pull-up.
RB4
bit4
TTL
Input/output pin (with interrupt-on-change).
Internal software programmable weak pull-up.
RB5/PGM⁽⁵⁾
RB6/PGC
RB7/PGD
bit5 TTL/ST⁽²⁾ Input/output pin (with interrupt-on-change).
Internal software programmable weak pull-up.
Low voltage ICSP enable pin.
bit6 TTL/ST⁽²⁾ Input/output pin (with interrupt-on-change).
Internal software programmable weak pull-up.
Serial programming clock.
bit7 TTL/ST⁽²⁾ Input/output pin (with interrupt-on-change).
Internal software programmable weak pull-up.
Serial programming data.
Legend: TTL = TTL input, ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: A device configuration bit selects which I/O pin the CCP2 pin is multiplexed on.
4: This buffer is a Schmitt Trigger input when configured as the CCP2 input.
5: Low Voltage ICSP Programming (LVP) is enabled by default, which disables the RB5 I/O function. LVP
must be disabled to enable RB5 as an I/O pin and allow maximum compatibility to the other 28-pin and
40-pin mid-range devices.
TABLE 9-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
PORTB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
LATB
LATB Data Output Register
TRISB
PORTB Data Direction Register
INTCON
GIE/
GIEH
PEIE/
GIEL
TMR0IE INT0IE RBIE TMR0IF INT0IF
INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP —
INTCON3 INT2IP INT1IP
—
INT2IE INT1IE
—
INT2IF
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.
RB0
RBIF
RBIP
INT1IF
xxxx xxxx
xxxx xxxx
1111 1111
0000 000x
1111 -1-1
11-0 0-00
Value on
All Other
RESETS
uuuu uuuu
uuuu uuuu
1111 1111
0000 000u
1111 -1-1
11-0 0-00
DS39564C-page 92
© 2006 Microchip Technology Inc.