PIC18LF252-ISP Datasheet, PDF (82/332 Pages) Microchip Technology – High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D

PIC18FXX2
8.3 PIE Registers
The PIE registers contain the individual enable bits for
the peripheral interrupts. Due to the number of periph-
eral interrupt sources, there are two Peripheral Inter-
rupt Enable Registers (PIE1, PIE2). When IPEN = 0,
the PEIE bit must be set to enable any of these
peripheral interrupts.
REGISTER 8-6:
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
R/W-0
PSPIE⁽¹⁾
bit 7
R/W-0
ADIE
R/W-0
RCIE
R/W-0
TXIE
R/W-0
SSPIE
R/W-0
CCP1IE
R/W-0
TMR2IE
R/W-0
TMR1IE
bit 0
bit 7
PSPIE⁽¹⁾: Parallel Slave Port Read/Write Interrupt Enable bit
1 = Enables the PSP read/write interrupt
0 = Disables the PSP read/write interrupt
bit 6
ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D interrupt
0 = Disables the A/D interrupt
bit 5
RCIE: USART Receive Interrupt Enable bit
1 = Enables the USART receive interrupt
0 = Disables the USART receive interrupt
bit 4
TXIE: USART Transmit Interrupt Enable bit
1 = Enables the USART transmit interrupt
0 = Disables the USART transmit interrupt
bit 3
SSPIE: Master Synchronous Serial Port Interrupt Enable bit
1 = Enables the MSSP interrupt
0 = Disables the MSSP interrupt
bit 2
CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 1
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
bit 0
TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
Note 1: This bit is reserved on PIC18F2X2 devices; always maintain this bit clear.
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
DS39564C-page 80
© 2006 Microchip Technology Inc.