PIC18LF252-ISP Datasheet, PDF (325/332 Pages) Microchip Technology – High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D

RETFIE ............................................................................ 242
RETLW ............................................................................. 242
RETURN .......................................................................... 243
Revision History ............................................................... 313
RLCF ................................................................................ 243
RLNCF ............................................................................. 244
RRCF ............................................................................... 244
RRNCF ............................................................................. 245
S
SCI. See USART
SCK .................................................................................. 125
SDI ................................................................................... 125
SDO ................................................................................. 125
Serial Clock, SCK ............................................................. 125
Serial Communication Interface. See USART
Serial Data In, SDI ........................................................... 125
Serial Data Out, SDO ....................................................... 125
Serial Peripheral Interface. See SPI
SETF ................................................................................ 245
Slave Select Synchronization ........................................... 131
Slave Select, SS .............................................................. 125
SLEEP ...............................................................195, 205, 246
Software Simulator (MPLAB SIM) .................................... 254
Special Event Trigger. See Compare
Special Features of the CPU ............................................ 195
Configuration Registers ................................... 196–201
Special Function Registers ................................................ 42
Map ............................................................................ 45
SPI
Master Mode ............................................................ 130
Serial Clock .............................................................. 125
Serial Data In ........................................................... 125
Serial Data Out ........................................................ 125
Slave Select ............................................................. 125
SPI Clock ................................................................. 130
SPI Mode ................................................................. 125
SPI Master/Slave Connection .......................................... 129
SPI Module
Associated Registers ............................................... 133
Bus Mode Compatibility ........................................... 133
Effects of a RESET .................................................. 133
Master/Slave Connection ......................................... 129
Slave Mode .............................................................. 131
Slave Select Synchronization .................................. 131
Slave Synch Timing ................................................. 131
SLEEP Operation ..................................................... 133
SS .................................................................................... 125
SSP
I²C Mode. See I²C
SPI Mode ................................................................. 125
SPI Mode. See SPI
SSPBUF Register .................................................... 130
SSPSR Register ...................................................... 130
TMR2 Output for Clock Shift ............................ 111, 112
SSPOV Status Flag .......................................................... 155
SSPSTAT Register
R/W Bit ............................................................. 138, 139
Status Bits
Significance and the Initialization Condition
for RCON Register ............................................. 27
SUBFWB .......................................................................... 246
SUBLW ............................................................................ 247
SUBWF ............................................................................ 247
SUBWFB .......................................................................... 248
SWAPF ............................................................................ 248
© 2006 Microchip Technology Inc.
PIC18FXX2
T
TABLAT Register ............................................................... 58
Table Pointer Operations (table) ........................................ 58
TBLPTR Register ............................................................... 58
TBLRD ............................................................................. 249
TBLWT ............................................................................. 250
Time-out Sequence ........................................................... 26
Time-out in Various Situations ................................... 27
Timer0 .............................................................................. 103
16-bit Mode Timer Reads and Writes ...................... 105
Associated Registers ............................................... 105
Clock Source Edge Select (T0SE Bit) ..................... 105
Clock Source Select (T0CS Bit) ............................... 105
Operation ................................................................. 105
Overflow Interrupt .................................................... 105
Prescaler. See Prescaler, Timer0
Timer1 .............................................................................. 107
16-bit Read/Write Mode ........................................... 109
Associated Registers ............................................... 110
Operation ................................................................. 108
Oscillator ...........................................................107, 109
Overflow Interrupt .............................................107, 109
Special Event Trigger (CCP) ............................109, 120
TMR1H Register ...................................................... 107
TMR1L Register ....................................................... 107
Timer2 .............................................................................. 111
Associated Registers ............................................... 112
Operation ................................................................. 111
Postscaler. See Postscaler, Timer2
PR2 Register ....................................................111, 122
Prescaler. See Prescaler, Timer2
SSP Clock Shift ................................................111, 112
TMR2 Register ......................................................... 111
TMR2 to PR2 Match Interrupt ................... 111, 112, 122
Timer3 .............................................................................. 113
Associated Registers ............................................... 115
Operation ................................................................. 114
Oscillator ...........................................................113, 115
Overflow Interrupt .............................................113, 115
Special Event Trigger (CCP) ................................... 115
TMR3H Register ...................................................... 113
TMR3L Register ....................................................... 113
Timing Diagrams
Bus Collision
Transmit and Acknowledge ..................... 159
A/D Conversion ........................................................ 287
Acknowledge Sequence .......................................... 158
Baud Rate Generator with Clock Arbitration ............ 152
BRG Reset Due to SDA Arbitration During
START Condition ............................................. 161
Brown-out Reset (BOR) ........................................... 274
Bus Collision
Start Condition (SDA Only) .............................. 160
Bus Collision During a Repeated
START Condition (Case 1) .............................. 162
Bus Collision During a Repeated
START Condition (Case 2) .............................. 162
Bus Collision During a START Condition
(SCL = 0) ......................................................... 161
Bus Collision During a STOP Condition
(Case 1) ........................................................... 163
Bus Collision During a STOP Condition
(Case 2) ........................................................... 163
Capture/Compare/PWM (CCP1 and CCP2) ............ 276
CLKO and I/O .......................................................... 272
Clock Synchronization ............................................. 145
DS39564C-page 323