PIC18LF252-ISP Datasheet, PDF(190/332 Page) Microchip Technology – High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D

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PIC18LF252-ISP Datasheet, PDF (190/332 Pages) Microchip Technology – High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D

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PIC18FXX2

17.5 Use of the CCP2 Trigger

An A/D conversion can be started by the âspecial event

triggerâ of the CCP2 module. This requires that the

CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be pro-

grammed as 1011 and that the A/D module is enabled

(ADON bit is set). When the trigger occurs, the GO/

DONE bit will be set, starting the A/D conversion, and

the Timer1 (or Timer3) counter will be reset to zero.

Timer1 (or Timer3) is reset to automatically repeat the

A/D acquisition period with minimal software overhead

(moving ADRESH/ADRESL to the desired location).

The appropriate analog input channel must be selected

and the minimum acquisition done before the âspecial

event triggerâ sets the GO/DONE bit (starts a

conversion).

If the A/D module is not enabled (ADON is cleared), the

âspecial event triggerâ will be ignored by the A/D

module, but will still reset the Timer1 (or Timer3)

counter.

TABLE 17-2: SUMMARY OF A/D REGISTERS

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR, BOR

Value on

All Other

RESETS

INTCON

PIR1

PIE1

IPR1

GIE/

GIEH

PSPIF(1)

PSPIE(1)

PSPIP(1)

PEIE/

GIEL

ADIF

ADIE

ADIP

TMR0IE

RCIF

RCIE

RCIP

INT0IE

TXIF

TXIE

TXIP

RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u

SSPIF

SSPIE

SSPIP

CCP1IF

CCP1IE

CCP1IP

TMR2IF

TMR2IE

TMR2IP

TMR1IF 0000 0000 0000 0000

TMR1IE 0000 0000 0000 0000

TMR1IP 0000 0000 0000 0000

PIR2

â

â

â

EEIF

BCLIF LVDIF TMR3IF CCP2IF ---0 0000 ---0 0000

PIE2

â

â

â

EEIE

BCLIE LVDIE TMR3IE CCP2IE ---0 0000 ---0 0000

IPR2

â

â

â

EEIP

BCLIP LVDIP TMR3IP CCP2IP ---1 1111 ---1 0000

ADRESH A/D Result Register

xxxx xxxx uuuu uuuu

ADRESL A/D Result Register

xxxx xxxx uuuu uuuu

ADCON0 ADCS1 ADCS0 CHS2

CHS1

CHS0 GO/DONE

â

ADON 0000 00-0 0000 00-0

ADCON1 ADFM ADCS2

â

â

PCFG3 PCFG2 PCFG1 PCFG0 ---- -000 ---- -000

PORTA

â

RA6

RA5

RA4

RA3

RA2

RA1

RA0 --0x 0000 --0u 0000

TRISA

â PORTA Data Direction Register

--11 1111 --11 1111

PORTE

â

â

â

â

â

RE2

RE1

RE0 ---- -000 ---- -000

LATE

â

â

â

â

â

LATE2 LATE1 LATE0 ---- -xxx ---- -uuu

TRISE

IBF

OBF

IBOV PSPMODE

â PORTE Data Direction bits

0000 -111 0000 -111

Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used for A/D conversion.

Note 1: The PSPIF, PSPIE and PSPIP bits are reserved on the PIC18F2X2 devices; always maintain these bits clear.

DS39564C-page 188

Â© 2006 Microchip Technology Inc.

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