PIC18LF252-ISP Datasheet, PDF (209/332 Pages) Microchip Technology – High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D

PIC18FXX2
19.4 Program Verification and
Code Protection
The overall structure of the code protection on the
PIC18 FLASH devices differs significantly from other
PICmicro devices.
The user program memory is divided into five blocks.
One of these is a boot block of 512 bytes. The remain-
der of the memory is divided into four blocks on binary
boundaries.
Each of the five blocks has three code protection bits
associated with them. They are:
• Code Protect bit (CPn)
• Write Protect bit (WRTn)
• External Block Table Read bit (EBTRn)
Figure 19-3 shows the program memory organization
for 16- and 32-Kbyte devices, and the specific code
protection bit associated with each block. The actual
locations of the bits are summarized in Table 19-3.
FIGURE 19-3:
CODE PROTECTED PROGRAM MEMORY FOR PIC18F2XX/4XX
MEMORY SIZE/DEVICE
16 Kbytes
(PIC18FX42)
32 Kbytes
(PIC18FX52)
Address
Range
Block Code Protection
Controlled By:
Boot Block
Block 0
Boot Block
Block 0
000000h
0001FFh
000200h
001FFFh
CPB, WRTB, EBTRB
CP0, WRT0, EBTR0
Block 1
Block 1
002000h
003FFFh
CP1, WRT1, EBTR1
Unimplemented
Read 0’s
Unimplemented
Read 0’s
Block 2
Block 3
004000h
005FFFh
006000h
007FFFh
CP2, WRT2, EBTR2
CP3, WRT3, EBTR3
008000h
Unimplemented
Read 0’s
Unimplemented
Read 0’s
(Unimplemented Memory Space)
1FFFFFh
TABLE 19-3: SUMMARY OF CODE PROTECTION REGISTERS
File Name
Bit 7
Bit 6
300008h CONFIG5L —
—
300009h CONFIG5H CPD
CPB
30000Ah CONFIG6L —
—
30000Bh CONFIG6H WRTD WRTB
30000Ch CONFIG7L —
—
30000Dh CONFIG7H —
EBTRB
Legend: Shaded cells are unimplemented.
Bit 5
—
—
—
WRTC
—
—
Bit 4
—
—
—
—
—
—
Bit 3
CP3
—
WRT3
—
EBTR3
—
Bit 2
CP2
—
WRT2
—
EBTR2
—
Bit 1
CP1
—
WRT1
—
EBTR1
—
Bit 0
CP0
—
WRT0
—
EBTR0
—
© 2006 Microchip Technology Inc.
DS39564C-page 207