PIC18LF252-ISP Datasheet, PDF (290/332 Pages) Microchip Technology – High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D

PIC18FXX2
TABLE 22-22: A/D CONVERSION REQUIREMENTS
Param
No.
Symbol
Characteristic
Min Max Units
Conditions
130 TAD
A/D clock period
PIC18FXXX
PIC18FXXX
1.6
20⁽⁴⁾
μs TOSC based
2.0
6.0
μs A/D RC mode
131 TCNV Conversion time
(not including acquisition time) (Note 1)
132 TACQ Acquisition time (Note 2)
135 TSWC Switching Time from convert → sample
11
12
TAD
5
—
μs VREF = VDD = 5.0V
10
—
μs VREF = VDD = 2.5V
— (Note 3)
Note 1: ADRES register may be read on the following TCY cycle.
2: The time for the holding capacitor to acquire the “New” input voltage, when the new input value has not
changed by more than 1 LSB from the last sampled voltage. The source impedance (RS) on the input channels
is 50Ω. See Section 17.0 for more information on acquisition time consideration.
3: On the next Q4 cycle of the device clock.
4: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.
DS39564C-page 288
© 2006 Microchip Technology Inc.