PIC18LF252-ISP Datasheet, PDF (160/332 Pages) Microchip Technology – High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D

PIC18FXX2
15.4.12 ACKNOWLEDGE SEQUENCE
TIMING
An Acknowledge sequence is enabled by setting the
Acknowledge sequence enable bit, ACKEN
(SSPCON2<4>). When this bit is set, the SCL pin is
pulled low and the contents of the Acknowledge data bit
are presented on the SDA pin. If the user wishes to gen-
erate an Acknowledge, then the ACKDT bit should be
cleared. If not, the user should set the ACKDT bit before
starting an Acknowledge sequence. The baud rate gen-
erator then counts for one rollover period (TBRG) and the
SCL pin is de-asserted (pulled high). When the SCL pin
is sampled high (clock arbitration), the baud rate gener-
ator counts for TBRG. The SCL pin is then pulled low. Fol-
lowing this, the ACKEN bit is automatically cleared, the
baud rate generator is turned off and the MSSP module
then goes into IDLE mode (Figure 15-23).
15.4.12.1 WCOL Status Flag
If the user writes the SSPBUF when an Acknowledge
sequence is in progress, then WCOL is set and the con-
tents of the buffer are unchanged (the write doesn’t occur).
15.4.13 STOP CONDITION TIMING
A STOP bit is asserted on the SDA pin at the end of a
receive/transmit by setting the STOP sequence enable
bit, PEN (SSPCON2<2>). At the end of a receive/trans-
mit the SCL line is held low after the falling edge of the
ninth clock. When the PEN bit is set, the master will
assert the SDA line low. When the SDA line is sampled
low, the baud rate generator is reloaded and counts
down to 0. When the baud rate generator times out, the
SCL pin will be brought high, and one TBRG (baud rate
generator rollover count) later, the SDA pin will be
de-asserted. When the SDA pin is sampled high while
SCL is high, the P bit (SSPSTAT<4>) is set. A TBRG
later, the PEN bit is cleared and the SSPIF bit is set
(Figure 15-24).
15.4.13.1 WCOL Status Flag
If the user writes the SSPBUF when a STOP sequence
is in progress, then the WCOL bit is set and the con-
tents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 15-23: ACKNOWLEDGE SEQUENCE WAVEFORM
Acknowledge sequence starts here,
Write to SSPCON2
ACKEN = 1, ACKDT = 0
ACKEN automatically cleared
SDA
TBRG
TBRG
D0
ACK
SCL
8
9
SSPIF
Set SSPIF at the end
of receive
Cleared in
software
Note: TBRG = one baud rate generator period.
Cleared in
software
Set SSPIF at the end
of Acknowledge sequence
FIGURE 15-24: STOP CONDITION RECEIVE OR TRANSMIT MODE
Write to SSPCON2
Set PEN
SCL = 1 for TBRG, followed by SDA = 1 for TBRG
after SDA sampled high. P bit (SSPSTAT<4>) is set.
Falling edge of
9th clock
SCL
TBRG
PEN bit (SSPCON2<2>) is cleared by
hardware and the SSPIF bit is set
SDA
ACK
TBRG
TBRG
P
TBRG
SCL brought high after TBRG
SDA asserted low before rising edge of clock
to setup STOP condition.
Note: TBRG = one baud rate generator period.
DS39564C-page 158
© 2006 Microchip Technology Inc.