PIC18LF252-ISP Datasheet, PDF (275/332 Pages) Microchip Technology – High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D

PIC18FXX2
TABLE 22-6: CLKO AND I/O TIMING REQUIREMENTS
Param.
No.
Symbol
Characteristic
Min
Typ
Max Units Conditions
10 TosH2ckL OSC1↑ to CLKO↓
—
75
200
ns (Note 1)
11
TosH2ckH OSC1↑ to CLKO↑
—
75
200
ns (Note 1)
12 TckR
CLKO rise time
—
35
100
ns (Note 1)
13 TckF
CLKO fall time
—
35
100
ns (Note 1)
14 TckL2ioV CLKO↓ to Port out valid
—
— 0.5 TCY + 20 ns (Note 1)
15 TioV2ckH Port in valid before CLKO ↑
0.25 TCY + 25 —
—
ns (Note 1)
16 TckH2ioI Port in hold after CLKO ↑
0
—
—
ns (Note 1)
17 TosH2ioV OSC1↑ (Q1 cycle) to Port out valid
—
50
150
ns
18 TosH2ioI OSC1↑ (Q2 cycle) to Port PIC18FXXX
100
—
—
ns
18A
input invalid (I/O in hold time) _PIC18LFXXX
200
—
—
ns
19 TioV2osH Port input valid to OSC1↑ (I/O in setup time)
0
—
—
ns
20 TioR
Port output rise time
PIC18FXXX
—
10
25
ns
20A
PIC18LFXXX
—
—
60
ns VDD = 2V
21 TioF
Port output fall time
PIC18FXXX
—
10
25
ns
21A
PIC18LFXXX
—
—
60
ns VDD = 2V
22†† TINP
INT pin high or low time
TCY
—
—
ns
23†† TRBP
RB7:RB4 change INT high or low time
TCY
—
—
ns
24†† TRCP
RC7:RC4 change INT high or low time
20
ns
†† These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken in RC mode, where CLKO output is 4 x TOSC.
FIGURE 22-7:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
Internal
POR
PWRT
Time-out
OSC
Time-out
Internal
Reset
Watchdog
Timer
Reset
33
32
I/O Pins
Note: Refer to Figure 22-4 for load conditions.
30
34
31
34
© 2006 Microchip Technology Inc.
DS39564C-page 273