PIC18LF252-ISP Datasheet, PDF (33/332 Pages) Microchip Technology – High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D

PIC18FXX2
TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
IPR2
242 442 252 452
---1 1111
---1 1111
---u uuuu
PIR2
242 442 252 452
---0 0000
---0 0000
---u uuuu⁽¹⁾
PIE2
242 442 252 452
---0 0000
---0 0000
---u uuuu
IPR1
242 442 252 452
242 442 252 452
1111 1111
-111 1111
1111 1111
-111 1111
uuuu uuuu
-uuu uuuu
PIR1
242 442 252 452
242 442 252 452
0000 0000
-000 0000
0000 0000
-000 0000
uuuu uuuu⁽¹⁾
-uuu uuuu⁽¹⁾
PIE1
242 442 252 452
242 442 252 452
0000 0000
-000 0000
0000 0000
-000 0000
uuuu uuuu
-uuu uuuu
TRISE
242 442 252 452
0000 -111
0000 -111
uuuu -uuu
TRISD
242 442 252 452
1111 1111
1111 1111
uuuu uuuu
TRISC
242 442 252 452
1111 1111
1111 1111
uuuu uuuu
TRISB
242 442 252 452
1111 1111
1111 1111
uuuu uuuu
TRISA^(5,6) 242 442 252 452
-111 1111⁽⁵⁾
-111 1111⁽⁵⁾
-uuu uuuu⁽⁵⁾
LATE
242 442 252 452
---- -xxx
---- -uuu
---- -uuu
LATD
242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
LATC
242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
LATB
242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
LATA^(5,6)
242 442 252 452
-xxx xxxx⁽⁵⁾
-uuu uuuu⁽⁵⁾
-uuu uuuu⁽⁵⁾
PORTE
242 442 252 452
---- -000
---- -000
---- -uuu
PORTD
242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTC
242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTB
242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTA^(5,6) 242 442 252 452
-x0x 0000⁽⁵⁾
-u0u 0000⁽⁵⁾
-uuu uuuu⁽⁵⁾
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 3-2 for RESET value for specific condition.
5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other
Oscillator modes, they are disabled and read ’0’.
6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ’0’.
© 2006 Microchip Technology Inc.
DS39564C-page 31