PIC18LF252-ISP Datasheet, PDF (93/332 Pages) Microchip Technology – High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D

FIGURE 9-5:
PIC18FXX2
BLOCK DIAGRAM OF RB2:RB0 PINS
RBPU⁽²⁾
Data Bus
WR Port
Data Latch
DQ
CK
VDD
P
Weak
Pull-up
I/O pin⁽¹⁾
WR TRIS
TRIS Latch
DQ
CK
TTL
Input
Buffer
RD TRIS
RD Port
QD
EN
RB0/INT
Schmitt Trigger
Buffer
RD Port
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).
FIGURE 9-6:
BLOCK DIAGRAM OF RB3 PIN
RBPU⁽²⁾
CCP2MX
CCP Output⁽³⁾
1
Enable⁽³⁾
CCP Output
Data Bus
WR LATB or
WR PORTB
WR TRISB
0
Data Latch
DQ
CK
TRIS Latch
D
CK _Q
VDD
P
Weak
Pull-up
VDD
P
N
VSS
TTL
Input
Buffer
I/O pin⁽¹⁾
RD TRISB
RD LATB
RD PORTB
Q
D
EN
RD PORTB
CCP2 Input⁽³⁾
Schmitt Trigger
Buffer
CCP2MX = 0
Note 1: I/O pin has diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate DDR bit(s) and clear the RBPU bit (INTCON2<7>).
3: The CCP2 input/output is multiplexed with RB3 if the CCP2MX bit is enabled (=’0’) in the configuration register.
© 2006 Microchip Technology Inc.
DS39564C-page 91