PIC18LF252-ISP Datasheet, PDF (273/332 Pages) Microchip Technology – High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D

PIC18FXX2
22.3.3 TIMING DIAGRAMS AND SPECIFICATIONS
FIGURE 22-5:
EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL)
Q4
Q1
Q2
Q3
Q4
Q1
OSC1
CLKO
1
3
3
4
4
2
TABLE 22-4: EXTERNAL CLOCK TIMING REQUIREMENTS
Param.
No.
Symbol
Characteristic
Min
Max Units
Conditions
1A
FOSC
External CLKI Frequency⁽¹⁾
DC
Oscillator Frequency⁽¹⁾
DC
DC
0.1
4
4
4
5
1
TOSC
External CLKI Period⁽¹⁾
25
Oscillator Period⁽¹⁾
40
40
MHz EC, ECIO, -40°C to +85°C
25
MHz EC, ECIO, +85°C to +125°C
4
MHz RC osc
4
MHz XT osc
25
MHz HS osc
10
MHz HS + PLL osc, -40°C to +85°C
6.25
MHz HS + PLL osc, +85°C to +125°C
200
kHz LP Osc mode
—
ns EC, ECIO, -40°C to +85°C
—
ns EC, ECIO, +85°C to +125°C
250
—
ns RC osc
250
10,000 ns XT osc
40
250
ns HS osc
100
250
ns HS + PLL osc, -40°C to +85°C
160
250
ns HS + PLL osc, +85°C to +125°C
25
—
μs LP osc
2
TCY
Instruction Cycle Time⁽¹⁾
100
—
ns TCY = 4/FOSC, -40°C to +85°C
160
—
ns TCY = 4/FOSC, +85°C to +125°C
3
TosL,
External Clock in (OSC1)
30
—
ns XT osc
TosH
High or Low Time
2.5
—
μs LP osc
10
—
ns HS osc
4
TosR, External Clock in (OSC1)
—
TosF
Rise or Fall Time
—
20
ns XT osc
50
ns LP osc
—
7.5
ns HS osc
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period for all configurations
except PLL. All specified values are based on characterization data for that particular oscillator type under
standard operating conditions with the device executing code. Exceeding these specified limits may result in
an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to
operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock input
is used, the “max.” cycle time limit is “DC” (no clock) for all devices.
© 2006 Microchip Technology Inc.
DS39564C-page 271