PIC18LF252-ISP Datasheet, PDF (279/332 Pages) Microchip Technology – High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D

FIGURE 22-11:
RE2/CS
PARALLEL SLAVE PORT TIMING (PIC18F4X2)
PIC18FXX2
RE0/RD
RE1/WR
65
RD7:RD0
64
Note: Refer to Figure 22-4 for load conditions.
62
63
TABLE 22-10: PARALLEL SLAVE PORT REQUIREMENTS (PIC18F4X2)
Param.
No.
Symbol
Characteristic
62
TdtV2wrH Data in valid before WR↑ or CS↑
(setup time)
63
TwrH2dtI WR↑ or CS↑ to data–in invalid PIC18FXXX
(hold time)
PIC18LFXXX
64
TrdL2dtV RD↓ and CS↓ to data–out valid
65
TrdH2dtI RD↑ or CS↓ to data–out invalid
66
TibfINH Inhibit of the IBF flag bit being cleared from
WR↑ or CS↑
Min Max Units
Conditions
20 — ns
25 — ns Extended Temp. Range
20 — ns
35 — ns VDD = 2V
— 80 ns
— 90 ns Extended Temp. Range
10 30 ns
— 3 TCY
© 2006 Microchip Technology Inc.
DS39564C-page 277