PIC18LF252-ISP Datasheet, PDF (120/332 Pages) Microchip Technology – High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D

PIC18FXX2
14.1 CCP1 Module
Capture/Compare/PWM Register 1 (CCPR1) is com-
prised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP1CON register controls
the operation of CCP1. All are readable and writable.
TABLE 14-1: CCP MODE - TIMER
RESOURCE
CCP Mode
Capture
Compare
PWM
Timer Resource
Timer1 or Timer3
Timer1 or Timer3
Timer2
14.2 CCP2 Module
Capture/Compare/PWM Register2 (CCPR2) is com-
prised of two 8-bit registers: CCPR2L (low byte) and
CCPR2H (high byte). The CCP2CON register controls
the operation of CCP2. All are readable and writable.
TABLE 14-2: INTERACTION OF TWO CCP MODULES
CCPx Mode CCPy Mode
Interaction
Capture
Capture
Compare
PWM
PWM
PWM
Capture
Compare
Compare
PWM
Capture
Compare
TMR1 or TMR3 time-base. Time-base can be different for each CCP.
The compare could be configured for the special event trigger,
which clears either TMR1 or TMR3 depending upon which time-base is used.
The compare(s) could be configured for the special event trigger,
which clears TMR1 or TMR3 depending upon which time-base is used.
The PWMs will have the same frequency and update rate
(TMR2 interrupt).
None
None
DS39564C-page 118
© 2006 Microchip Technology Inc.