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| PIC18LF252-ISP Datasheet, PDF (32/332 Pages) Microchip Technology – High-Performance, Enhanced Flash Microcontrollers with 10-Bit A/D | |||
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PIC18FXX2
TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
ADRESH 242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
ADRESL
242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
ADCON0 242 442 252 452
0000 00-0
0000 00-0
uuuu uu-u
ADCON1 242 442 252 452
00-- 0000
00-- 0000
uu-- uuuu
CCPR1H 242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR1L
242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP1CON 242 442 252 452
--00 0000
--00 0000
--uu uuuu
CCPR2H 242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR2L
242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP2CON 242 442 252 452
--00 0000
--00 0000
--uu uuuu
TMR3H
242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR3L
242 442 252 452
xxxx xxxx
uuuu uuuu
uuuu uuuu
T3CON
242 442 252 452
0000 0000
uuuu uuuu
uuuu uuuu
SPBRG
242 442 252 452
0000 0000
0000 0000
uuuu uuuu
RCREG
242 442 252 452
0000 0000
0000 0000
uuuu uuuu
TXREG
242 442 252 452
0000 0000
0000 0000
uuuu uuuu
TXSTA
242 442 252 452
0000 -010
0000 -010
uuuu -uuu
RCSTA
242 442 252 452
0000 000x
0000 000x
uuuu uuuu
EEADR
242 442 252 452
0000 0000
0000 0000
uuuu uuuu
EEDATA
242 442 252 452
0000 0000
0000 0000
uuuu uuuu
EECON1 242 442 252 452
xx-0 x000
uu-0 u000
uu-0 u000
EECON2 242 442 252 452
---- ----
---- ----
---- ----
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 3-2 for RESET value for specific condition.
5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO Oscillator modes only. In all other
Oscillator modes, they are disabled and read â0â.
6: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read â0â.
DS39564C-page 30
© 2006 Microchip Technology Inc.
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