PIC32MX1XX_12 Datasheet, PDF (78/328 Pages) Microchip Technology – 32-bit Microcontrollers (up to 128 KB Flash and 32 KB SRAM) with Audio and Graphics Interfaces, USB, and Advanced Analog

PIC32MX1XX/2XX
REGISTER 5-1: NVMCON: PROGRAMMING CONTROL REGISTER
Bit
Range
31:24
23:16
15:8
7:0
Bit
31/23/15/7
U-0
—
U-0
—
R/W-0
WR
U-0
—
Bit
30/22/14/6
U-0
—
U-0
—
R/W-0
WREN
U-0
—
Bit
29/21/13/5
U-0
—
U-0
—
R-0
WRERR⁽¹⁾
U-0
—
Bit
Bit
28/20/12/4 27/19/11/3
U-0
U-0
—
—
U-0
U-0
—
—
R-0
R-0
LVDERR⁽¹⁾ LVDSTAT⁽¹⁾
U-0
R/W-0
—
Bit
Bit
26/18/10/2 25/17/9/1
U-0
U-0
—
—
U-0
U-0
—
—
U-0
U-0
—
—
R/W-0
R/W-0
NVMOP<3:0>
Bit
24/16/8/0
U-0
—
U-0
—
U-0
—
R/W-0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16 Unimplemented: Read as ‘0’
bit 15 WR: Write Control bit
This bit is writable when WREN = 1 and the unlock sequence is followed.
1 = Initiate a Flash operation. Hardware clears this bit when the operation completes
0 = Flash operation complete or inactive
bit 14 WREN: Write Enable bit
1 = Enable writes to WR bit and enables LVD circuit
0 = Disable writes to WR bit and disables LVD circuit
This is the only bit in this register reset by a device Reset.
bit 13 WRERR: Write Error bit⁽¹⁾
This bit is read-only and is automatically set by hardware.
1 = Program or erase sequence did not complete successfully
0 = Program or erase sequence completed normally
bit 12 LVDERR: Low-Voltage Detect Error bit (LVD circuit must be enabled)⁽¹⁾
This bit is read-only and is automatically set by hardware.
1 = Low-voltage detected (possible data corruption, if WRERR is set)
0 = Voltage level is acceptable for programming
bit 11 LVDSTAT: Low-Voltage Detect Status bit (LVD circuit must be enabled)⁽¹⁾
This bit is read-only and is automatically set, and cleared, by hardware.
1 = Low-voltage event active
0 = Low-voltage event NOT active
bit 10-4 Unimplemented: Read as ‘0’
bit 3-0 NVMOP<3:0>: NVM Operation bits
These bits are writable when WREN = 0.
1111 = Reserved
•
•
•
0111 = Reserved
0110 = No operation
0101 = Program Flash (PFM) erase operation: erases PFM, if all pages are not write-protected
0100 = Page erase operation: erases page selected by NVMADDR, if it is not write-protected
0011 = Row program operation: programs row selected by NVMADDR, if it is not write-protected
0010 = No operation
0001 = Word program operation: programs word selected by NVMADDR, if it is not write-protected
0000 = No operation
Note 1: This bit is cleared by setting NVMOP == 0000b, and initiating a Flash operation (i.e., WR).
DS61168E-page 78
Preliminary
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