PIC32MX1XX_12 Datasheet, PDF (110/328 Pages) Microchip Technology – 32-bit Microcontrollers (up to 128 KB Flash and 32 KB SRAM) with Audio and Graphics Interfaces, USB, and Advanced Analog

PIC32MX1XX/2XX
REGISTER 9-8: DCHxECON: DMA CHANNEL ‘x’ EVENT CONTROL REGISTER
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
31:24
23:16
15:8
7:0
U-0
—
R/W-1
R/W-1
S-0
CFORCE
U-0
—
R/W-1
R/W-1
S-0
CABORT
U-0
—
R/W-1
R/W-1
R/W-0
PATEN
U-0
U-0
—
—
R/W-1
R/W-1
CHAIRQ<7:0>⁽¹⁾
R/W-1
R/W-1
CHSIRQ<7:0>⁽¹⁾
R/W-0
R/W-0
SIRQEN AIRQEN
U-0
—
R/W-1
R/W-1
U-0
—
U-0
—
R/W-1
R/W-1
U-0
—
Bit
24/16/8/0
U-0
—
R/W-1
R/W-1
U-0
—
Legend:
R = Readable bit
-n = Value at POR
S = Settable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-24 Unimplemented: Read as ‘0’
bit 23-16 CHAIRQ<7:0>: Channel Transfer Abort IRQ bits⁽¹⁾
11111111 = Interrupt 255 will abort any transfers in progress and set CHAIF flag
•
•
•
00000001 = Interrupt 1 will abort any transfers in progress and set CHAIF flag
00000000 = Interrupt 0 will abort any transfers in progress and set CHAIF flag
bit 15-8 CHSIRQ<7:0>: Channel Transfer Start IRQ bits⁽¹⁾
11111111 = Interrupt 255 will initiate a DMA transfer
•
•
•
00000001 = Interrupt 1 will initiate a DMA transfer
00000000 = Interrupt 0 will initiate a DMA transfer
bit 7
CFORCE: DMA Forced Transfer bit
1 = A DMA transfer is forced to begin when this bit is written to a ‘1’
0 = This bit always reads ‘0’
bit 6
CABORT: DMA Abort Transfer bit
1 = A DMA transfer is aborted when this bit is written to a ‘1’
0 = This bit always reads ‘0’
bit 5
PATEN: Channel Pattern Match Abort Enable bit
1 = Abort transfer and clear CHEN on pattern match
0 = Pattern match is disabled
bit 4
SIRQEN: Channel Start IRQ Enable bit
1 = Start channel cell transfer if an interrupt matching CHSIRQ occurs
0 = Interrupt number CHSIRQ is ignored and does not start a transfer
bit 3
AIRQEN: Channel Abort IRQ Enable bit
1 = Channel transfer is aborted if an interrupt matching CHAIRQ occurs
0 = Interrupt number CHAIRQ is ignored and does not terminate a transfer
bit 2-0 Unimplemented: Read as ‘0’
Note 1: See Table 7-1: “Interrupt IRQ, Vector and Bit Location” for the list of available interrupt IRQ sources.
DS61168E-page 110
Preliminary
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