PIC32MX1XX_12 Datasheet, PDF (193/328 Pages) Microchip Technology – 32-bit Microcontrollers (up to 128 KB Flash and 32 KB SRAM) with Audio and Graphics Interfaces, USB, and Advanced Analog

PIC32MX1XX/2XX
REGISTER 20-1: RTCCON: RTC CONTROL REGISTER (CONTINUED)
bit 5-4 Unimplemented: Read as ‘0’
bit 3
RTCWREN: RTC Value Registers Write Enable bit⁽⁴⁾
1 = RTC Value registers can be written to by the user
0 = RTC Value registers are locked out from being written to by the user
bit 2
RTCSYNC: RTCC Value Registers Read Synchronization bit
1 = RTC Value registers can change while reading, due to a rollover ripple that results in an invalid data read
If the register is read twice and results in the same data, the data can be assumed to be valid
0 = RTC Value registers can be read without concern about a rollover ripple
bit 1
HALFSEC: Half-Second Status bit⁽⁵⁾
1 = Second half period of a second
0 = First half period of a second
bit 0
RTCOE: RTCC Output Enable bit
1 = RTCC clock output enabled – clock presented onto an I/O
0 = RTCC clock output disabled
Note 1:
2:
3:
4:
5:
The ON bit is only writable when RTCWREN = 1.
When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
Requires RTCOE = 1 (RTCCON<0>) for the output to be active.
The RTCWREN bit can be set only when the write sequence is enabled.
This bit is read-only. It is cleared to ‘0’ on a write to the seconds bit fields (RTCTIME<14:8>).
Note: This register is reset only on a Power-on Reset (POR).
 2011-2012 Microchip Technology Inc.
Preliminary
DS61168E-page 193