PIC32MX1XX_12 Datasheet, PDF (175/328 Pages) Microchip Technology – 32-bit Microcontrollers (up to 128 KB Flash and 32 KB SRAM) with Audio and Graphics Interfaces, USB, and Advanced Analog

PIC32MX1XX/2XX
REGISTER 17-2: I2CXSTAT: I²C™ STATUS REGISTER
Bit
Bit
Bit
Bit
Bit
Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3
31:24
23:16
15:8
7:0
U-0
—
U-0
—
R-0, HSC
ACKSTAT
R/C-0, HS
IWCOL
U-0
—
U-0
—
R-0, HSC
TRSTAT
R/C-0, HS
I2COV
U-0
—
U-0
—
U-0
—
R-0, HSC
D_A
U-0
—
U-0
—
U-0
—
R/C-0, HSC
P
U-0
—
U-0
—
U-0
—
R/C-0, HSC
S
Bit
26/18/10/2
U-0
—
U-0
—
R/C-0, HS
BCL
R-0, HSC
R_W
Bit
25/17/9/1
U-0
—
U-0
—
R-0, HSC
GCSTAT
R-0, HSC
RBF
Bit
24/16/8/0
U-0
—
U-0
—
R-0, HSC
ADD10
R-0, HSC
TBF
Legend:
R = Readable bit
-n = Value at POR
HS = Set in hardware
W = Writable bit
‘1’ = Bit is set
HSC = Hardware set/cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
C = Clearable bit
bit 31-16 Unimplemented: Read as ‘0’
bit 15
ACKSTAT: Acknowledge Status bit
(when operating as I²C™ master, applicable to master transmit operation)
bit 14
1 = NACK received from slave
0 = ACK received from slave
Hardware set or clear at end of slave Acknowledge.
TRSTAT: Transmit Status bit (when operating as I²C master, applicable to master transmit operation)
1 = Master transmit is in progress (8 bits + ACK)
0 = Master transmit is not in progress
Hardware set at beginning of master transmission. Hardware clear at end of slave Acknowledge.
bit 13-11 Unimplemented: Read as ‘0’
bit 10 BCL: Master Bus Collision Detect bit
1 = A bus collision has been detected during a master operation
0 = No collision
Hardware set at detection of bus collision.
bit 9
GCSTAT: General Call Status bit
1 = General call address was received
0 = General call address was not received
Hardware set when address matches general call address. Hardware clear at Stop detection.
bit 8
ADD10: 10-bit Address Status bit
1 = 10-bit address was matched
0 = 10-bit address was not matched
Hardware set at match of 2nd byte of matched 10-bit address. Hardware clear at Stop detection.
bit 7
IWCOL: Write Collision Detect bit
1 = An attempt to write the I2CxTRN register failed because the I²C module is busy
0 = No collision
Hardware set at occurrence of write to I2CxTRN while busy (cleared by software).
bit 6
I2COV: Receive Overflow Flag bit
1 = A byte was received while the I2CxRCV register is still holding the previous byte
0 = No overflow
Hardware set at attempt to transfer I2CxRSR to I2CxRCV (cleared by software).
bit 5
D_A: Data/Address bit (when operating as I²C slave)
1 = Indicates that the last byte received was data
0 = Indicates that the last byte received was device address
Hardware clear at device address match. Hardware set by reception of slave byte.
 2011-2012 Microchip Technology Inc.
Preliminary
DS61168E-page 175