English
Language : 

PIC32MX1XX_12 Datasheet, PDF (155/328 Pages) Microchip Technology – 32-bit Microcontrollers (up to 128 KB Flash and 32 KB SRAM) with Audio and Graphics Interfaces, USB, and Advanced Analog
◁
PIC32MX1XX/2XX
REGISTER 13-1: TXCON: TYPE B TIMER CONTROL REGISTER
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2
U-0
31:24
—
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
U-0
23:16
—
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
R/W-0
U-0
R/W-0
U-0
U-0
U-0
15:8
ON(1,3)
—
SIDL(4)
—
—
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
7:0
TGATE(3)
TCKPS<2:0>(3)
T32(2)
—
Bit
25/17/9/1
U-0
—
U-0
—
U-0
—
R/W-0
TCS(3)
Bit
24/16/8/0
U-0
—
U-0
—
U-0
—
U-0
—
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-16
bit 15
bit 14
bit 13
bit 12-8
bit 7
bit 6-4
Unimplemented: Read as ‘0’
ON: Timer On bit(1,3)
1 = Module is enabled
0 = Module is disabled
Unimplemented: Read as ‘0’
SIDL: Stop in Idle Mode bit(4)
1 = Discontinue operation when device enters Idle mode
0 = Continue operation even in Idle mode
Unimplemented: Read as ‘0’
TGATE: Timer Gated Time Accumulation Enable bit(3)
When TCS = 1:
This bit is ignored and is read as ‘0’.
When TCS = 0:
1 = Gated time accumulation is enabled
0 = Gated time accumulation is disabled
TCKPS<2:0>: Timer Input Clock Prescale Select bits(3)
111 = 1:256 prescale value
110 = 1:64 prescale value
101 = 1:32 prescale value
100 = 1:16 prescale value
011 = 1:8 prescale value
010 = 1:4 prescale value
001 = 1:2 prescale value
000 = 1:1 prescale value
Note 1:
2:
3:
4:
When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
This bit is available only on even numbered timers (Timer2 and Timer4).
While operating in 32-bit mode, this bit has no effect for odd numbered timers (Timer1, Timer3, and
Timer5). All timer functions are set through the even numbered timers.
While operating in 32-bit mode, this bit must be cleared on odd numbered timers to enable the 32-bit timer
in Idle mode.
 2011-2012 Microchip Technology Inc.
Preliminary
DS61168E-page 155
 ▷