PIC32MX1XX_12 Datasheet, PDF(139/328 Page) Microchip Technology – 32-bit Microcontrollers (up to 128 KB Flash and 32 KB SRAM) with Audio and Graphics Interfaces, USB, and Advanced Analog

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PIC32MX1XX_12 Datasheet, PDF (139/328 Pages) Microchip Technology – 32-bit Microcontrollers (up to 128 KB Flash and 32 KB SRAM) with Audio and Graphics Interfaces, USB, and Advanced Analog

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PIC32MX1XX/2XX

REGISTER 10-21: U1EP0-U1EP15: USB ENDPOINT CONTROL REGISTER

Bit

Bit

Bit

Bit

Bit

Bit

Bit

Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2

U-0

U-0

U-0

U-0

U-0

U-0

31:24

â

â

â

â

â

â

U-0

U-0

U-0

U-0

U-0

U-0

23:16

â

â

â

â

â

â

U-0

U-0

U-0

U-0

U-0

U-0

15:8

â

â

â

â

â

â

R/W-0

R/W-0

U-0

R/W-0

R/W-0

R/W-0

7:0

LSPD RETRYDIS

â

EPCONDIS EPRXEN EPTXEN

Bit

25/17/9/1

U-0

â

U-0

â

U-0

â

R/W-0

EPSTALL

Bit

24/16/8/0

U-0

â

U-0

â

U-0

â

R/W-0

EPHSHK

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

â1â = Bit is set

U = Unimplemented bit, read as â0â

â0â = Bit is cleared

x = Bit is unknown

bit 31-8 Unimplemented: Read as â0â

bit 7 LSPD: Low-Speed Direct Connection Enable bit (Host mode and U1EP0 only)

1 = Direct connection to a low-speed device enabled

0 = Direct connection to a low-speed device disabled; hub required with PRE_PID

bit 6 RETRYDIS: Retry Disable bit (Host mode and U1EP0 only)

1 = Retry NAKâd transactions disabled

0 = Retry NAKâd transactions enabled; retry done in hardware

bit 5 Unimplemented: Read as â0â

bit 4 EPCONDIS: Bidirectional Endpoint Control bit

If EPTXEN = 1 and EPRXEN = 1:

1 = Disable Endpoint n from Control transfers; only TX and RX transfers allowed

0 = Enable Endpoint n for Control (SETUP) transfers; TX and RX transfers also allowed

Otherwise, this bit is ignored.

bit 3 EPRXEN: Endpoint Receive Enable bit

1 = Endpoint n receive enabled

0 = Endpoint n receive disabled

bit 2 EPTXEN: Endpoint Transmit Enable bit

1 = Endpoint n transmit enabled

0 = Endpoint n transmit disabled

bit 1 EPSTALL: Endpoint Stall Status bit

1 = Endpoint n was stalled

0 = Endpoint n was not stalled

bit 0 EPHSHK: Endpoint Handshake Enable bit

1 = Endpoint Handshake enabled

0 = Endpoint Handshake disabled (typically used for isochronous endpoints)

ï£ 2011-2012 Microchip Technology Inc.

Preliminary

DS61168E-page 139

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