PIC32MX1XX_12 Datasheet, PDF (287/328 Pages) Microchip Technology – 32-bit Microcontrollers (up to 128 KB Flash and 32 KB SRAM) with Audio and Graphics Interfaces, USB, and Advanced Analog

PIC32MX1XX/2XX
TABLE 30-3: DC CHARACTERISTICS: IDLE CURRENT (IIDLE)
DC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
Parameter
No.
Typical⁽²⁾
Max.
Units
Conditions
Idle Current (IIDLE): Core Off, Clock on Base Current (Note 1)
MDC34a
8
13
mA
50 MHz
Note 1: The test conditions for IIDLE current measurements are as follows:
• Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by
external square wave from rail-to-rail, (OSC1 input clock input over/undershoot < 100 mV required)
• OSC2/CLKO is configured as an I/O input pin
• USB PLL oscillator is disabled if the USB module is implemented, PBCLK divisor = 1:8
• CPU is in Idle mode (CPU core Halted), and SRAM data memory Wait states = 1
• No peripheral modules are operating, (ON bit = 0), but the associated PMD bit is cleared
• WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled
• All I/O pins are configured as inputs and pulled to VSS
• MCLR = VDD
• RTCC and JTAG are disabled
2: Data in the “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
TABLE 30-4: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)
DC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
Param.
No.
Typical⁽²⁾
Max.
Units
Conditions
Power-Down Current (IPD) (Note 1)
MDC40k 10
25
A
MDC40n 250
500
A
-40°C
+85°C
Base Power-Down Current
Module Differential Current
MDC41e 10
55
A
MDC42e 23
55
A
MDC43d 1100
1300
A
3.6V
3.6V
3.6V
Watchdog Timer Current: IWDT (Note 3)
RTCC + Timer1 w/32 kHz Crystal: IRTCC (Note 3)
ADC: IADC (Notes 3,4)
Note 1:
2:
3:
4:
The test conditions for IPD current measurements are as follows:
• Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by
external square wave from rail-to-rail, (OSC1 input clock input over/undershoot < 100 mV required)
• OSC2/CLKO is configured as an I/O input pin
• USB PLL oscillator is disabled if the USB module is implemented, PBCLK divisor = 1:8
• CPU is in Sleep mode, and SRAM data memory Wait states = 1
• No peripheral modules are operating, (ON bit = 0), but the associated PMD bit is set
• WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled
• All I/O pins are configured as inputs and pulled to VSS
• MCLR = VDD
• RTCC and JTAG are disabled
Data in the “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
The  current is the additional current consumed when the module is enabled. This current should be
added to the base IPD current.
Test conditions for ADC module differential current are as follows: Internal ADC RC oscillator enabled.
 2011-2012 Microchip Technology Inc.
Preliminary
DS61168E-page 287