PIC32MX1XX_12 Datasheet, PDF (31/328 Pages) Microchip Technology – 32-bit Microcontrollers (up to 128 KB Flash and 32 KB SRAM) with Audio and Graphics Interfaces, USB, and Advanced Analog

PIC32MX1XX/2XX
3.0 CPU
Note 1: This data sheet summarizes the features
of the PIC32MX1XX/2XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 2. “CPU”
(DS61113) in the “PIC32 Family
Reference Manual”, which is available
from the Microchip web site
(www.microchip.com/PIC32). Resources
for the MIPS32^® M4K^® Processor Core
are available at: www.mips.com.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The the MIPS32^® M4K^® Processor Core is the heart of
the PIC32MX1XX/2XX family processor. The CPU
fetches instructions, decodes each instruction, fetches
source operands, executes each instruction and writes
the results of instruction execution to the proper
destinations.
3.1 Features
• 5-stage pipeline
• 32-bit address and data paths
• MIPS32^® Enhanced Architecture (Release 2)
- Multiply-accumulate and multiply-subtract
instructions
- Targeted multiply instruction
- Zero/One detect instructions
- WAIT instruction
- Conditional move instructions (MOVN, MOVZ)
- Vectored interrupts
- Programmable exception vector base
- Atomic interrupt enable/disable
- Bit field manipulation instructions
• MIPS16e^® code compression
- 16-bit encoding of 32-bit instructions to improve
code density
- Special PC-relative instructions for efficient load-
ing of addresses and constants
- SAVE and RESTORE macro instructions for setting
up and tearing down stack frames within subrou-
tines
- Improved support for handling 8 and 16-bit data
types
• Simple Fixed Mapping Translation (FMT)
mechanism
• Simple dual bus interface
- Independent 32-bit address and data busses
- Transactions can be aborted to improve interrupt
latency
• Autonomous multiply/divide unit
- Maximum issue rate of one 32x16 multiply per
clock
- Maximum issue rate of one 32x32 multiply every
other clock
- Early-in iterative divide. Minimum 11 and maxi-
mum 33 clock latency (dividend (rs) sign exten-
sion-dependent)
• Power control
- Minimum frequency: 0 MHz
- Low-Power mode (triggered by WAIT instruction)
- Extensive use of local gated clocks
• EJTAG debug and instruction trace
- Support for single stepping
- Virtual instruction and data address/value
- Breakpoints
FIGURE 3-1:
MIPS32^® M4K^® PROCESSOR CORE BLOCK DIAGRAM
CPU
MDU
EJTAG
TAP
Off-chip Debug Interface
Execution Core
(RF/ALU/Shift)
FMT
Bus Interface
Dual Bus Interface _{Bus Matrix}
System
Co-processor
Power
Management
 2011-2012 Microchip Technology Inc.
Preliminary
DS61168E-page 31