PIC16LF1454 Datasheet, PDF (318/418 Pages) Microchip Technology – 14/20-Pin Flash, 8-Bit USB Microcontrollers with XLP Technology

PIC16(L)F1454/5/9
26.5 USB Interrupts
The USB module can generate multiple interrupt
conditions. To accommodate all of these interrupt
sources, the module is provided with its own interrupt
logic structure, similar to that of the microcontroller.
USB interrupts are enabled with one set of control
registers and trapped with a separate set of flag
registers. All sources are funneled into a single USB
interrupt request, USBIF bit of the PIR2 for use with the
microcontroller's interrupt logic.
Figure 26-6 shows the interrupt logic for the USB
module, which is divided into two registers in the USB
module. USB status interrupts are considered the top
level and interrupts are enabled through the UIE
register, while flags are maintained through the UIF
register. USB error conditions are considered the
second level and interrupts are enabled through the
UEIE register, while flags are maintained through the
UEIF register. Any USB interrupt condition will trigger
the USB Error Interrupt Flag, the UERRIF bit of the UIF
register.
Interrupts may be used to trap routine events in a USB
transaction. Figure 26-7 shows some common events
within a USB frame and their corresponding interrupts.
FIGURE 26-6:
USB INTERRUPT LOGIC FUNNEL
Second Level USB Interrupts
(USB Error Conditions)
UEIR (Flag) and UEIE (Enable) Registers
Top Level USB Interrupts
(USB Status Interrupts)
UIR (Flag) and UIE (Enable) Registers
BTSEF
BTSEE
BTOEF
BTOEE
DFN8EF
DFN8EE
CRC16EF
CRC16EE
CRC5EF
CRC5EE
PIDEF
PIDEE
SOFIF
SOFIE
TRNIF
TRNIE
IDLEIF
IDLEIE
UERRIF
UERRIE
STALLIF
STALLIE
ACTVIF
ACTVIE
USBIF
URSTIF
URSTIE
FIGURE 26-7:
EXAMPLE OF A USB TRANSACTION AND INTERRUPT EVENTS
From Host From Host
SETUP Token Data
To Host
ACK
USB Reset
URSTIF
Start-of-Frame (SOF)
SOFIF
From Host
IN Token
To Host
Data
From Host
ACK
From Host From Host
OUT Token Empty Data
Transaction
To Host
ACK
Set TRNIF
Set TRNIF
Set TRNIF
Transaction
Complete
RESET
Differential Data
SOF
SETUP DATA STATUS
Control Transfer⁽¹⁾
SOF
1 ms Frame
Note 1: The control transfer shown here is only an example showing events that can occur for every transaction. Typical control transfers
will spread across multiple frames.
DS41639A-page 318
Preliminary
 2012 Microchip Technology Inc.