PIC16LF1454 Datasheet, PDF (315/418 Pages) Microchip Technology – 14/20-Pin Flash, 8-Bit USB Microcontrollers with XLP Technology

PIC16(L)F1454/5/9
TABLE 26-1: EFFECT OF DTSEN BIT ON ODD/EVEN (DATA0/DATA1) PACKET RECEPTION
OUT Packet
from Host
BDnSTAT Settings
DTSEN
DTS
Device Response after Receiving Packet
Handshake UOWN TRNIF BDnSTAT and USTAT Status
DATA0
1
DATA1
1
DATA0
1
DATA1
1
Either
0
Either, with error
x
Legend: x = don’t care
0
ACK
0
1
0
ACK
1
0
1
ACK
1
0
1
ACK
0
1
x
ACK
0
1
x
NAK
1
0
Updated
Not Updated
Not Updated
Updated
Updated
Not Updated
26.4.1.3 BDnSTAT Register (SIE Mode)
When the BD and its buffer are owned by the SIE, most
of the bits in BDnSTAT take on a different meaning. The
configuration is shown in Register 26-6. Once the
UOWN bit is set, any data or control settings previously
written there by the user will be overwritten with data
from the SIE.
The BDnSTAT register is updated by the SIE with the
token Packet Identifier (PID), which is stored in the PID
bits of the BDnSTAT register. The transfer count in the
corresponding BDnCNT register is updated. Values
that overflow the 8-bit register carry over to the two
Most Significant digits of the count, BD bits of the
BDnSTAT register.
26.4.2 BD BYTE COUNT
The byte count represents the total number of bytes
that will be transmitted during an IN transfer. After an IN
transfer, the SIE will return the number of bytes sent to
the host.
For an OUT transfer, the byte count represents the
maximum number of bytes that can be received and
stored in USB RAM. After an OUT transfer, the SIE will
return the actual number of bytes received. If the
number of bytes received exceeds the corresponding
byte count, the data packet will be rejected and a NAK
handshake will be generated. When this happens, the
byte count will not be updated.
The 10-bit byte count is distributed over two registers.
The lower 8 bits of the count reside in the BDnCNT reg-
ister. The upper two bits reside in the BC bits of the
BDnSTAT register. This represents a valid byte range
of 0 to 1023.
26.4.3 BD ADDRESS VALIDATION
The BD Address register pair contains the starting RAM
address location for the corresponding endpoint buffer.
No mechanism is available in hardware to validate the
BD address.
If the value of the BD address does not point to an
address in the USB RAM, or if it points to an address
within another endpoint's buffer, data is likely to be lost
or overwritten. Similarly, overlapping a receive buffer
(OUT endpoint) with a BD location in use can yield
unexpected results. When developing USB applications,
the user may want to consider the inclusion of software-
based address validation in their code.
26.4.4 PING-PONG BUFFERING
An endpoint is defined to have a ping-pong buffer when
it has two sets of BD entries: one set for an Even
transfer and one set for an Odd transfer. This allows the
CPU to process one BD while the SIE is processing the
other BD. Double-buffering BDs in this way allows for
maximum throughput to/from the USB.
The USB module supports four modes of operation:
• No ping-pong support
• Ping-pong buffer support for OUT Endpoint 0 only
• Ping-pong buffer support for all endpoints
• Ping-pong buffer support for all other Endpoints
except Endpoint 0
The ping-pong buffer settings are configured using the
PPB bits in the UCFG register.
The USB module keeps track of the Ping-Pong Pointer
individually for each endpoint. All pointers are initially
reset to the Even BD when the module is enabled. After
the completion of a transaction (UOWN cleared by the
SIE), the pointer is toggled to the Odd BD. After the
completion of the next transaction, the pointer is
toggled back to the Even BD and so on.
The Even/Odd status of the last transaction is stored in
the PPBI bit of the USTAT register. The user can reset
all Ping-Pong Pointers to Even using the PPBRST bit.
Figure 26-5 shows the four different modes of opera-
tion and how USB RAM is filled with the BDs. BDs have
a fixed relationship to a particular endpoint depending
on the buffering configuration. The mapping of BDs to
endpoints is detailed in Table 26-2. This relationship
also means that gaps may occur in the BDT if end-
points are not enabled contiguously. This theoretically
means that the BDs for disabled endpoints could be
used as buffer space. In practice, users should avoid
using such spaces in the BDT unless a method of vali-
dating BD addresses is implemented.
 2012 Microchip Technology Inc.
Preliminary
DS41639A-page 315