PIC16LF1454 Datasheet, PDF (314/418 Pages) Microchip Technology – 14/20-Pin Flash, 8-Bit USB Microcontrollers with XLP Technology

PIC16(L)F1454/5/9
FIGURE 26-4:
EXAMPLE OF A BUFFER
DESCRIPTOR
2000h
2001h
2002h
2003h
2080h
BD0STAT
BD0CNT
BD0ADRL
BD0ADRH
(xxh)
(40h)
(80h)
(20h)
Size of Block
Starting
Address
Buffer
USB Data
20BFh
Note: Memory regions not to scale.
26.4.1 BD STATUS AND CONFIGURATION
The USB Data memory ownership and the BDnSTAT
bits change functionality depending on the UOWN bit
level.
Unlike other control registers, the bit configuration for
the BDnSTAT register is context sensitive determined
by the UOWN bit. If the UOWN bit is clear, the
microcontroller has the ability to modify the BD and its
corresponding buffer. If the UOWN bit is set, the USB
SIE has the ability to modify the BD and its
corresponding buffer. The UOWN, BC9 and BC8 bit
definitions are contained within the BDnSTAT register,
regardless of the UOWN bit value.
26.4.1.1 Buffer Ownership
A simple semaphore mechanism is used to distinguish
if the CPU or USB module is allowed to update the BD
and associated buffers in memory, which is shared by
both.
The UOWN bit of the BDnSTAT register is used as a
semaphore to distinguish if the USB or CPU is allowed
to update the BD and associated buffers in memory.
Only the UOWN bit shares functionality between the
two configurations of the BDnSTAT register.
When the UOWN bit is clear, the BD entry and buffer
memory are “owned” by the microcontroller core. When
the UOWN bit is set, these are “owned” by the USB
peripheral. The BD and corresponding buffers should
only be modified by the “owner”. However, the
BDnSTAT register can be read by either the
microcontroller or the USB, even if they are not the
“owner”.
Because the buffer descriptor meanings are based
upon the source of the register update, the user must
configure the basic operation of the USB peripheral
through the BDnSTAT register prior to placing
ownership with the USB peripheral. While still owned
by the microcontroller, the byte count and buffer
location registers must also be set.
When the UOWN bit is set, giving ownership to the
USB peripheral, the SIE updates the BDs as
necessary, overwriting the original BD values. Thus,
values written by the user to BD are no longer
dependable. Instead, the BDnSTAT register is updated
automatically by the SIE with the token PID and
transfer count (BDnCNT).
The BDnSTAT byte of the BDT should always be the
last byte updated when preparing to arm an endpoint.
The SIE will clear the UOWN bit when a transaction
has completed.
Because no hardware mechanism exists to block
access to the memory, unexpected behavior can occur
if the microcontroller attempts to modify memory while
the SIE owns it. Also, reading the memory may
produce inaccurate data until the USB peripheral
returns ownership to the microcontroller.
26.4.1.2 BDnSTAT Register (CPU Mode)
When UOWN = 0, the microcontroller core owns the
BD and the other bits of the register become control
functions.
The Data Toggle Sync Enable (DTSEN) bit of the
BDnSTAT register controls data toggle parity checking
and, when set, enables data toggle synchronization by
the SIE. When enabled, the DTSEN checks the data
packet's parity against the value of the Data Toggle
Synchronization (DTS) bit. Packets incorrectly
synchronized are ignored and will not be written to the
USB RAM. The USB TRNIF bit will not be set.
However, the SIE will send an ACK token to the host to
acknowledge receipt. Refer to Table 26-1 for the effects
of the DTSEN bit on the SIE.
The Buffer Stall bit, BSTALL of the BDnSTAT register,
provides support for control transfers, usually one-time
stalls on Endpoint 0. It also provides support for the
SET_FEATURE/CLEAR_FEATURE
commands
specified in Chapter 9 of the USB specification.
Typically, these commands are executed by continuous
STALLs to any endpoint other than the default control
endpoint.
The BSTALL bit enables buffer stalls. Setting BSTALL
causes the SIE to return a STALL token to the host if a
received token would use the BD in that location. The
EPSTALL bit in the corresponding UEPn control
register is set and a STALL interrupt is generated when
a STALL is issued to the host. The UOWN bit remains
set and the BDs are not changed unless a SETUP
token is received. In this case, the STALL condition is
cleared and the ownership of the BD is returned to the
microcontroller core.
The BD bits of the BDnSTAT register store the two Most
Significant digits of the SIE byte count; the lower 8 digits
are stored in the corresponding BDnCNT register. See
Section 26.4.2 “BD Byte Count” for more information.
DS41639A-page 314
Preliminary
 2012 Microchip Technology Inc.