PIC16LF1454 Datasheet, PDF (30/418 Pages) Microchip Technology – 14/20-Pin Flash, 8-Bit USB Microcontrollers with XLP Technology

TABLE 3-4: PIC16(L)F1454 MEMORY MAP, BANK 0-7
BANK 0
BANK 1
BANK 2
BANK 3
000h
Core Registers
(Table 3-2)
080h
Core Registers
(Table 3-2)
100h
Core Registers
(Table 3-2)
180h
Core Registers
(Table 3-2)
00Bh
00Ch
00Dh
00Eh
00Fh
010h
011h
012h
013h
014h
015h
016h
017h
018h
019h
01Ah
01Bh
01Ch
01Dh
01Eh
01Fh
020h
PORTA
—
PORTC
—
—
PIR1
PIR2
—
—
TMR0
TMR1L
TMR1H
T1CON
T1GCON
TMR2
PR2
T2CON
—
—
—
08Bh
08Ch
08Dh
08Eh
08Fh
090h
091h
092h
093h
094h
095h
096h
097h
098h
099h
09Ah
09Bh
09Ch
09Dh
09Eh
09Fh
0A0h
TRISA
—
TRISC
—
—
PIE1
PIE2
—
—
OPTION_REG
PCON
WDTCON
OSCTUNE
OSCCON
OSCSTAT
—
—
—
—
—
10Bh
10Ch
10Dh
10Eh
10Fh
110h
111h
112h
113h
114h
115h
116h
117h
118h
119h
11Ah
11Bh
11Ch
11Dh
11Eh
11Fh
120h
LATA
—
LATC
—
—
—
—
—
—
—
BORCON
—
—
—
—
—
—
APFCON
—
—
18Bh
18Ch
18Dh
18Eh
18Fh
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
19Ah
19Bh
19Ch
19Dh
19Eh
19Fh
1A0h
—
—
—
—
—
PMADRL
PMADRH
PMDATL
PMDATH
PMCON1
PMCON2
VREGCON
—
RCREG
TXREG
SPBRG
SPBRGH
RCSTA
TXSTA
BAUDCON
Dual-Port
General
Purpose
Register
80 Bytes
Dual-Port
General
Purpose
Register
80 Bytes
Dual-Port
General
Purpose
Register
80 Bytes
Dual-Port
General
Purpose
Register
80 Bytes
06Fh
070h
07Fh
Dual-Port
Common RAM
0EFh
0F0h
0FFh
Common RAM
(Accesses
70h – 7Fh)
16Fh
170h
17Fh
Common RAM
(Accesses
70h – 7Fh)
1EFh
1F0h
1FFh
Common RAM
(Accesses
70h – 7Fh)
200h
20Bh
20Ch
20Dh
20Eh
20Fh
210h
211h
212h
213h
214h
215h
216h
217h
218h
219h
21Ah
21Bh
21Ch
21Dh
21Eh
21Fh
220h
26Fh
270h
27Fh
BANK 4
Core Registers
(Table 3-2)
WPUA
—
—
—
—
SSP1BUF
SSP1ADD
SSP1MSK
SSP1STAT
SSP1CON1
SSP1CON2
SSP1CON3
—
—
—
—
—
—
—
—
Dual-Port
General
Purpose
Register
80 Bytes
Common RAM
(Accesses
70h – 7Fh)
280h
28Bh
28Ch
28Dh
28Eh
28Fh
290h
291h
292h
293h
294h
295h
296h
297h
298h
299h
29Ah
29Bh
29Ch
29Dh
29Eh
29Fh
2A0h
2EFh
2F0h
2FFh
BANK 5
Core Registers
(Table 3-2)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Dual-Port
General
Purpose
Register
80 Bytes
Common RAM
(Accesses
70h – 7Fh)
300h
30Bh
30Ch
30Dh
30Eh
30Fh
310h
311h
312h
313h
314h
315h
316h
317h
318h
319h
31Ah
31Bh
31Ch
31Dh
31Eh
31Fh
320h
32Fh
330h
36Fh
370h
37Fh
BANK 6
Core Registers
(Table 3-2)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Dual-Port
General
Purpose
Register
16Bytes
General
Purpose
Register
64 Bytes
Common RAM
(Accesses
70h – 7Fh)
380h
38Bh
38Ch
38Dh
38Eh
38Fh
390h
391h
392h
393h
394h
395h
396h
397h
398h
399h
39Ah
39Bh
39Ch
39Dh
39Eh
39Fh
3A0h
3EFh
3F0h
3FFh
BANK 7
Core Registers
(Table 3-2)
—
—
—
—
—
IOCAP
IOCAN
IOCAF
—
—
—
—
—
—
CLKRCON
CRCON
—
—
—
—
General
Purpose
Register
80 Bytes
Common RAM
(Accesses
70h – 7Fh)
Legend:
= Unimplemented data memory locations, read as ‘0’.