PIC16LF1454 Datasheet, PDF(213/418 Page) Microchip Technology – 14/20-Pin Flash, 8-Bit USB Microcontrollers with XLP Technology

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PIC16LF1454 Datasheet, PDF (213/418 Pages) Microchip Technology – 14/20-Pin Flash, 8-Bit USB Microcontrollers with XLP Technology

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PIC16(L)F1454/5/9

22.2.6 SPI OPERATION IN SLEEP MODE

In SPI Master mode, module clocks may be operating

at a different speed than when in full power mode; in

the case of the Sleep mode, all clocks are halted.

Special care must be taken by the user when the MSSP

clock is much faster than the system clock.

In Slave mode, when MSSP interrupts are enabled,

after the master completes sending data, an MSSP

interrupt will wake the controller from Sleep.

If an exit from Sleep mode is not desired, MSSP inter-

rupts should be disabled.

In SPI Master mode, when the Sleep mode is selected,

all module clocks are halted and the transmis-

sion/reception will remain in that state until the device

wakes. After the device returns to Run mode, the mod-

ule will resume transmitting and receiving data.

In SPI Slave mode, the SPI Transmit/Receive Shift

register operates asynchronously to the device. This

allows the device to be placed in Sleep mode and data

to be shifted into the SPI Transmit/Receive Shift

register. When all eight bits have been received, the

MSSP interrupt flag bit will be set and if enabled, will

wake the device.

TABLE 22-1: SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ANSELA(3)

â

â

â

ANSA4

â

â

â

â

INTCON

PIE1

PIR1

GIE

TMR1GIE

TMR1GIF

PEIE

ADIE(3)

ADIF(3)

TMR0IE

RCIE

RCIF

INTE

TXIE

TXIF

IOCIE

SSP1IE

SSP1IF

TMR0IF

â

â

INTF

TMR2IE

TMR2IF

IOCIF

TMR1IE

TMR1IF

SSP1BUF Synchronous Serial Port Receive Buffer/Transmit Register

SSP1CON1 WCOL

SSPOV SSPEN

CKP

SSPM<3:0>

SSP1CON3 ACKTIM

PCIE

SCIE

BOEN

SDAHT

SBCDE

AHEN

DHEN

SSP1STAT

TRISA

TRISC

SMP

â

TRISC7(2)

CKE

â

TRISC6(2)

D/A

TRISA5

TRISC5

P

TRISA4

TRISC4

S

â(1)

TRISC3

R/W

â

TRISC2

UA

â(1)

TRISC1

BF

â(1)

TRISC0

Legend:

*

Note 1:

2:

3:

â = Unimplemented location, read as â0â. Shaded cells are not used by the MSSP in SPI mode.

Page provides register information.

Unimplemented, read as â1â.

PIC16(L)F1459 only.

PIC16(L)F1455/9 only.

Register

on Page

133

96

97

99

207*

253

255

251

132

140

ï£ 2012 Microchip Technology Inc.

Preliminary

DS41639A-page 213

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