PIC16LF1454 Datasheet, PDF (310/418 Pages) Microchip Technology – 14/20-Pin Flash, 8-Bit USB Microcontrollers with XLP Technology

PIC16(L)F1454/5/9
26.2 USB Status and Control
The operation of the USB module is configured and
managed through three control registers. In addition, a
total of 14 registers are used to manage the actual USB
transactions. The registers are:
• USB Control register (UCON)
• USB Configuration register (UCFG)
• USB Transfer Status register (USTAT)
• USB Device Address register (UADDR)
• Frame Number registers (UFRMH:UFRML)
• Endpoint Enable registers 0 through 7 (UEPn)
26.2.1 USB CONTROL (UCON) REGISTER
The USB Control register (Register 26-1) contains bits
needed to control the module behavior during
transfers. The register contains bits that control the
following:
• Main USB Peripheral Enable
• Ping-Pong Buffer Pointer Reset
• Control of the Suspend mode
• Packet Transfer Disable
The SE0 bit of the UCON register is used to indicate the
occurrence of a single-ended zero on the bus. When
the USB module is enabled, this bit should be
monitored to determine whether the differential data
lines have come out of a single-ended zero condition.
This helps to differentiate the initial power-up state from
the USB Reset signal.
The USBEN bit of the UCON register is used to enable
and disable the module. Setting this bit activates the
module and resets all of the PPBI bits in the Buffer
Descriptor Table to ‘0’. If enabled, this bit will also
activate the USB internal pull-up resistors. Thus, this bit
can be used as a soft attach/detach to the USB. The
USB module needs to be supplied with an active clock
source before the USBEN bit can be set. Also, the USB
module needs to be fully preconfigured prior to
enabling the USB module.
Note:
If the PLL is being used, wait until the
PLLRDY bit is set in the OSCSTAT register
before attempting to set the USBEN bit.
The PPBRST bit of the UCON register controls the
Reset status when Double-Buffering mode (ping-pong
buffering) is used. When the PPBRST bit is set, all
Ping-Pong Buffer Pointers are set to the Even buffers.
The PPBRST bit must be cleared by firmware. This bit
is ignored in buffering modes not using ping-pong
buffering.
The PKTDIS bit of the UCON register is a flag indicating
that the SIE has disabled packet transmission and
reception. This bit is set by the SIE when a SETUP token
is received to allow setup processing. This bit cannot be
set by the microcontroller, only cleared. Clearing the bit
to ‘0’ allows the SIE to continue transmission and/or
reception. Any pending events within the Buffer
Descriptor Table will still be available, indicated within
the USTAT register's FIFO buffer ENDP bits.
The RESUME bit of the UCON register configures the
peripheral to perform a remote wake-up by executing
Resume signaling. To generate a valid remote wake-up,
firmware must set the RESUME bit for 10 ms and then
automatically clear the bit. For more information on
“resume signaling”, see the USB 2.0 specification.
The SUSPND bit of the UCON register places the
module and supporting circuitry in a Low-Power mode.
The input clock to the SIE is also disabled. This bit must
be set by the firmware in response to an IDLEIF
interrupt. It should be reset by the microcontroller
firmware after an ACTVIF interrupt is observed. When
this bit is active, the device remains attached to the bus
but the transceiver outputs remain Idle. The voltage on
the VUSB3V3 pin may vary depending on the value of
this bit. Setting this bit before a IDLEIF request will
result in unpredictable bus behavior.
Note:
While in Suspend mode, a typical bus-
powered USB device is limited to the
suspend current discussed in the USB 2.0
specification Chapter 7.2.3. This is the
complete current, which may be drawn by
the microcontroller and its supporting
circuitry. Care should be taken to assure
minimum current draw when the device
enters Suspend mode.
26.2.2 USB CONFIGURATION (UCFG)
REGISTER
The UCFG register (Register 26-2) is used in
configuring system level behavior of the USB module.
All internal and external hardware should be configured
prior to attempting communications. The UCFG
register is used for the following USB functions:
• Bus Speed (Full/Low Speed)
• On-Chip Pull-up Resistor Enable
• Ping-Pong Buffer Usage
The UTEYE bit of the UCFG register enables the eye
pattern generation. This bit aids in module testing,
debugging and USB certification processes. Refer to
26.2.2.4 “Eye Pattern Test Enable” for more detail.
Note:
The USB speed, transceiver and pull-up
should only be configured during the mod-
ule setup phase. It is not recommended to
switch these settings while the module is
enabled.
DS41639A-page 310
Preliminary
 2012 Microchip Technology Inc.