PIC16LF1454 Datasheet, PDF (312/418 Pages) Microchip Technology – 14/20-Pin Flash, 8-Bit USB Microcontrollers with XLP Technology

PIC16(L)F1454/5/9
26.2.3 USB STATUS (USTAT) REGISTER
The USB Status register (Register 26-3) reports the
transaction status within the SIE. When the SIE issues
a USB transaction complete interrupt (TRNIF bit),
USTAT should be read to determine the status of the
transfer. USTAT contains the transfer endpoint number,
direction and Ping-Pong Buffer Pointer value (if used).
Note:
The data in the USB Status register is
valid two SIE clocks after the TRNIF bit is
asserted.
In low-speed operation with the system
clock operating at 48 MHz, a delay may
be required between receiving the trans-
action complete interrupt and processing
the data in the USTAT register.
The USTAT register is actually a read window into a
four-byte status FIFO, maintained by the SIE. It allows
the microcontroller to process one transfer while the
SIE processes additional endpoints (Figure 26-2).
When the SIE completes using a buffer for reading or
writing data, it updates the USTAT register. If another
USB transfer is performed before the TRNIF bit is
serviced, the SIE will store the status of the next
transaction into the status FIFO.
Clearing the TRNIF bit advances the FIFO. If the next
data in the FIFO holding register is valid, the SIE will
reassert the interrupt within 6 TCY of clearing the
TRNIF bit. If no additional data is present, the TRNIF bit
will remain clear; USTAT data will no longer be reliable.
Note:
If an endpoint request is received while
the USTAT FIFO is full, the SIE will
automatically issue a NAK back to the
host.
FIGURE 26-2:
USTAT FIFO
USTAT from SIE
4-Byte FIFO
for USTAT
Data Bus
Clearing TRNIF
Advances FIFO
26.2.4 USB ENDPOINT CONTROL (UEPN)
REGISTER
Each bidirectional endpoint pair has its own
independent control register, UEPn (where 'n'
represents the endpoint number). Each register has an
identical complement of control bits (see Register 26-4).
The EPHSHK bit configures the USB handshaking for
the endpoint. Typically, this bit is always set except
when using isochronous endpoints.
The EPCONDIS bit configures the USB control
operations through the endpoint. Clearing this bit
enables SETUP transactions. The corresponding
EPINEN and EPOUTEN bits must be set to enable IN
and OUT transactions.
Note:
For Endpoint 0, the EPCONDIS bit should
always be cleared since the USB
specifications identify Endpoint 0 as the
default control endpoint.
The EPOUTEN bit configures USB OUT transactions
from the host. Setting this bit enables OUT
transactions. Similarly, the EPINEN bit is used to
configure the USB IN transactions from the host.
The EPSTALL bit indicates a STALL condition for the
endpoint. If a STALL is issued on a particular endpoint,
the EPSTALL bit for that endpoint pair will be set by the
SIE. This bit remains set until it is cleared through
firmware, or until the SIE is reset.
26.2.5 USB ADDRESS (UADDR) REGISTER
The USB Address register contains the unique USB
address that the peripheral will decode when active.
The UADDR register is reset to 00h when a USB Reset
is received, indicated by the USB Reset Interrupt bit
(URSTIF), or when a Reset is received from the micro-
controller. The USB address must be written in
response to the USB SET_ADDRESS request.
26.2.6 USB FRAME NUMBER REGISTERS
(UFRMH:UFRML)
The Frame Number registers contain the 11-bit frame
number. The low-order byte is contained in UFRML,
while the three high-order bits are contained in
UFRMH. The register pair is updated with the current
frame number whenever a SOF token is received. For
the microcontroller, these registers are read-only. The
Frame Number registers are primarily used for
isochronous transfers. The contents of the UFRMH and
UFRML registers are only valid when the 48 MHz SIE
clock is active (i.e., contents are inaccurate when
SUSPND bit of the UCON register is set).
DS41639A-page 312
Preliminary
 2012 Microchip Technology Inc.