IS75V16F128GS32 Datasheet, PDF (7/52 Pages) Integrated Silicon Solution, Inc – 3.0 Volt Multi-Chip Package (MCP) 128 Mbit Simultaneous Operation Flash Memory and 32 Mbit Pseudo Static RAM

IS75V16F128GS32
DC CHARACTERISTICS (Continued)
ISSI ^®
Symbol Parameter
Test Conditions
Min. Typ.
Max. Unit
IPD8r PSRAM VCC Power
Down Current
(8M Partial)⁽⁸⁾
VCCr = VCCr max.,
CE1r ≥ VCCr - 0.2 V
—
—
80
µA
CE2r ≤ 0.2 V, VIN Cycle time = tRC min
VIL
VIH
VIH
VID
VACC
Input Low Level
Input High Level (FLASH 1 or FLASH 2 )
Input High Level (PSRAM)
Voltage for Sector Protection
and Temp. Unprotection(RESET)⁽⁴⁾
Voltage for WP/ACC
Sector Protection/Unprotection
and Program Acceleration ⁽⁴⁾
-0.3 —
0.5
V
VCCf X 0.75 — VCCf + 0.3
V
VCCr X 0.75 — VCCr + 0.3
V
11.5 —
12.5
V
8.5 9.0
9.5
V
VOL
VOH
VOL
VOH
VLKO
Output Low Level
(PSRAM)
Output High Level
(PSRAM)
Output Low Level
(Flash)
Output High Level
(Flash)
FLASH Low Vccf
Lock-Out Voltage
VCCr = VCCr min., VCCS=VCCS min.
IOL = 1.0 mA
—
—
0.4
V
VCCr = VCCr min., VCCS=VCCS min.
2.2 —
—
V
IOH = -0.5 mA
VCCf = VCCf min., VCCS=VCCS min.
IOL = 4.0 mA
—
—
0.45
V
VCCf = VCCf min., VCCS=VCCS min.
VCCf - 0.4 —
—
V
IOH = -0.1 mA
2.3 2.4
2.5
V
Notes:
1. ICC current listed includes both the DC operating current and the frequency dependent component.
2. ICC active while Embedded Algorithm (program or erase) is in progress.
3. Automatic sleep mode enables the low power mode when address remains stable for 150 ns.
4. Applicable for only VCCf applying.
5. Embedded Algorithm (program or erase) is in progress. (@5 MHz)
6. ISB2 r depends on VIN cycle time. Please refer to “APPENDIX A”.
7. Standby current listed is for each FLASH chip.
8. Standby and Power down currents are reduced with Vccr ^< 3.0 V .
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
7
PRELIMINARY INFORMATION Rev. 00D
03/24/03