IS75V16F128GS32 Datasheet, PDF (26/52 Pages) Integrated Silicon Solution, Inc – 3.0 Volt Multi-Chip Package (MCP) 128 Mbit Simultaneous Operation Flash Memory and 32 Mbit Pseudo Static RAM

IS75V16F128GS32
FLASH WRITE CYCLE - FLASH 1 or FLASH 2
(WE CONTROL)
ISSI ^®
ADDRESS
3rd Bus Cycle
555h
PA
tWC
tAS tAH
CEf
tCS
OE
tGHWL
tCH
tWP tWPH
WE
tDS tDH
A0h
PD
DQ
Data Polling
tRC
PA
tWHWH1
tCE
tOE
tDF
DQ7 Dout
tOH
Dout
Notes:
1. PA is address of the memory location to be programmed.
2. PD is data to be programmed at byte address.
3. DQ7 is the output of the complement of the data written to the device.
4. DOUT is the output of the data written to the device.
5. Figure indicates last two bus cycles out of four bus cycle sequence.
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Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
03/24/03