IS75V16F128GS32 Datasheet, PDF (21/52 Pages) Integrated Silicon Solution, Inc – 3.0 Volt Multi-Chip Package (MCP) 128 Mbit Simultaneous Operation Flash Memory and 32 Mbit Pseudo Static RAM

IS75V16F128GS32
ISSI ^®
FLASH READ ONLY OPERATIONS CHARACTERISTICS - FLASH 1 or FLASH 2
Parameter
JEDEC
Symbol
Read Cycle Time
tAVAV
Address to Output Delay
tAVQV
Chip Enable to Output Delay
tELQV
Output Enable to Output Delay
tGLQV
Chip Enable to Output High-Z
tEHQZ
Output Enable to Output High-Z
tGHQZ
Output Hold Time From Addresses, tAXQX
CEf or OE, Whichever Occurs First
RESET Pin Low to Read Mode
—
Test Conditions:
Output Load : 1 TTL gate and 30 pF
Input rise and fall times : 5 ns
Input pulse levels : 0.0 V or VCCf
Timing measurement reference level
Input : VCCf/2
Output : VCCf/2
Standard
Symbol
tRC
tACC
tCE
tOE
tDF
tDF
tOH
Condition
Min Max
70 —
CEf = VIL, OE = VIL — 70
OE = VIL
— 70
— 30
— 25
— 25
0—
Unit
ns
ns
ns
ns
ns
ns
ns
tREADY
— 20
µs
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
21
PRELIMINARY INFORMATION Rev. 00D
03/24/03