IS75V16F128GS32 Datasheet, PDF (4/52 Pages) Integrated Silicon Solution, Inc – 3.0 Volt Multi-Chip Package (MCP) 128 Mbit Simultaneous Operation Flash Memory and 32 Mbit Pseudo Static RAM

IS75V16F128GS32
ISSI ^®
DEVICE BUS OPERATION
OPERATION^(1,2)
Full Standby
Output Disable⁽³⁾
CEf1 CEf2
HH
HH
LH
HL
CE1r CE2r OE WE LBs UBs PE A₂₁-A₀ DQ₇-DQ₀ DQ₁₅-DQ₈ RESET1 RESET2 WP/ACC⁽¹²⁾
H H X XX XH X
High-Z High-Z
H
H
X
L H H H X X H X⁽¹⁰⁾ High-Z High-Z
H
H
X
H H H HX XH X
High-Z High-Z
H
H
X
H H H HX XH X
High-Z High-Z
H
H
X
Read from FLASH 1⁽⁴⁾L H
HH
L H X X H Valid DOUT DOUT
H
H
X
Read from FLASH 2⁽⁴⁾H L
HH
L H X X H Valid
DOUT DOUT
H
H
X
Write to FLASH 1 L H
H H H L X X H Valid
DIN
DIN
H
H
X
Write to FLASH 2 H L
H H H L X X H Valid
DIN
DIN
H
H
X
Read from PSRAM⁽⁵⁾ H H
LH
L H L⁽⁹⁾ L⁽⁹⁾ H Valid
DOUT DOUT
H
H
X
Write to PSRAM H H
L H H L L L H Valid
DIN
DIN
H
H
X
HH
L H H L H L H Valid High-Z DIN
H
H
X
HH
L H H L L H H Valid
DIN High-Z
H
H
X
FLASH 1Temporary
Sector Group
X X X X X XX XX X
X
X
VID
X
X
Unprotection⁽⁶⁾
FLASH 2 Temporary
Sector Group
X X X X X XX XX X
X
X
X
VID
X
Unprotection⁽⁶⁾
FLASH 1
Hardware Reset
XX
H H X XX XX X
High-Z High-Z
L
X
X
FLASH 2
Hardware Reset
XX
H H X XX XX X
High-Z High-Z
X
L
X
Boot Block Sector
Write Protection X X X X X X X X X X
X
X
X
X
L
PSRAM Power⁽⁷⁾
Down Program
H H H H X X X X L Valid High-Z High-Z
H
H
X
PSRAM No Read H H L H L H H H H Valid High-Z High-Z
H
H
X
PSRAM
Power Down⁽⁸⁾
X X X L X XX XX X
X
X
X
X
X
Legend : L = VIL, H = VIH, X = VIL or VIH. See “DC CHARACTERISTICS” for voltage levels.
Notes:
1. Other operations except for indicated this column are prohibited.
2. Do not apply CEf = VIL, CE1r = VIL and CE2r = VIH all at once.
3. PSRAM Output Disable condition should not be kept longer than 1ms.
4. WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
5. PSRAM LB,UB control at Read operation is not supported.
6. It is also used for the extended sector group protections.
7. The PSRAM Power Down Program can be performed one time after compliance of Power-UP timings and it should not be re-
programmed after regular Read or Write.
8. PSRAM Power Down mode can be entered from Standby state and all DQ pins are in High-Z state. IPDr current and data retention
depends on the selection of Power Down Program.
9. Either or both LB and UB must be Low for PSRAM Read Operation.
10. Can be either VIL or VIH but must be valid before Read or Write.
11. See “ PSRAM Power Down Program Key Table “ located in the next page.
12. Protect “ outer most “ 2x8K bytes ( 4 words ) on both ends of the boot block sectors.
4
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
03/24/03