IS75V16F128GS32 Datasheet, PDF (42/52 Pages) Integrated Silicon Solution, Inc – 3.0 Volt Multi-Chip Package (MCP) 128 Mbit Simultaneous Operation Flash Memory and 32 Mbit Pseudo Static RAM

IS75V16F128GS32
PSRAM READ TIMING (Address Access after OE Control Access)
ADDRESS
(A20-A3)
tRC
ADDRESS VALID
tRC
ADDRESS VALID
(No Change)
ISSI ^®
ADDRESS
(A2-A0)
CE1r
OE
ADDRESS VALID
tASO
tOLAH
tOE
ADDRESS VALID
tAA
tAX
tOHAH
tOHZ
LB / UB
tBSO
tOHBH
DQ
(Output)
tOLZ
tOH
tOH
VALID DATA OUTPUT
VALID DATA OUTPUT
Note: CE2r, PE and WE must be High during read cycle. Either or both LB and UB must be Low when both CE1r and OE are Low.
PSRAM READ TIMING (Address Access after CE1r Control Access)
ADDRESS
(A20-A3)
tRC
ADDRESS VALID
tRC
ADDRESS VALID
(No Change)
ADDRESS
(A2-A0)
CE1r
OE
tASC
ADDRESS VALID
tCLAH
tAX
ADDRESS VALID
tAA
tCHAH
tCHZ
tCE
tBSC
UB, LB
tCHBH
DQ
(Output)
tCLZ
tOH
tOH
VALID DATA OUTPUT
VALID DATA OUTPUT
Note: CE2r, PE and WE must be High during read cycle. Either or both LB and UB must be Low when both CE1r and OE are Low.
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Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00D
03/24/03