IS75V16F128GS32 Datasheet, PDF (45/52 Pages) Integrated Silicon Solution, Inc – 3.0 Volt Multi-Chip Package (MCP) 128 Mbit Simultaneous Operation Flash Memory and 32 Mbit Pseudo Static RAM

IS75V16F128GS32
ISSI ^®
PSRAM READ / WRITE TIMING (CE1r Control)
ADDRESS
CE1r
WE
UB, LB
OE
tWRC
tASC
tRC
Read Address
tCHAH
Write Address
tAS
tWRC (Min)
tWH
tWS
tCE
tBSC
tBH
tCP
tWH
tWS
tCHBH
tBS
tOEH
tOHCL
DQ
tDH
tCLZ
tCHZ
tOH
Write Data Input
Read Data Output
Note: The tOEH is specified from the time satisfied oth tWRC and tWR(min).
PSRAM READ / WRITE TIMING (READ = OE Control, WRITE = WE Control)
ADDRESS
CE1r ^Low
WE
UB, LB
tWC
Write Address
tOHAH
tAS
tAH
Read Address
tASO
tOHBH tBS
tWP
tWR
tOEH
tBH
tBSO
OE
tOES
DQ
tOH
tOHZ
tDS
tDH
tOLZ
Read Data Output
Write Data Input
Note: CE1r can be tied to Low for WE and OE controlled operation. When CE1r is tied to Low, output is
exclusively controlled by OE.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
45
PRELIMINARY INFORMATION Rev. 00D
03/24/03