BD82HM55-SLGZS Datasheet, PDF (93/956 Pages) Intel Corporation – Intel® 5 Series Chipset and Intel® 3400 Series Chipset

Signal Description
2.28 Pin Straps
2.28.1 Functional Straps
The following signals are used for static configuration. They are sampled at the rising
edge of PWROK to select configurations (except as noted), and then revert later to their
normal usage. To invoke the associated mode, the signal should be driven at least four
PCI clocks prior to the time it is sampled.
The PCH has implemented Soft Straps. Soft Straps are used to configure specific
functions within the PCH and processor very early in the boot process before BIOS or
SW intervention. When Descriptor Mode is enabled, the PCH will read Soft Strap data
out of the SPI device prior to the de-assertion of reset to both the Management Engine
and the Host system. See Section 5.24.2 for information on Descriptor Mode.
Table 2-28. Functional Strap Definitions (Sheet 1 of 4)
Signal
Usage
When
Sampled
Comment
The signal has a weak internal pull-down.
SPKR
INIT3_3V#
GNT[3]#/
GPIO[55]
INTVRMEN
No Reboot
Reserved
Top-Block
Swap Override
Integrated 1.05
V VRM Enable /
Disable
Rising edge of
PWROK
Rising edge of
PWROK
Rising edge of
PWROK
Always
NOTE: The internal pull-down is disabled after PLTRST# de-
asserts. If the signal is sampled high, this indicates
that the system is strapped to the “No Reboot”
mode (the PCH will disable the TCO Timer system
reboot feature). The status of this strap is readable
using the NO REBOOT bit (Chipset Config Registers:
Offset 3410h:bit 5).
This signal has a weak internal pull up. Note that the
internal pull-up is disabled after PLTRST# de-asserts.
NOTE: This signal should not be pulled low.
The signal has a weak internal pull-up. If the signal is
sampled low, this indicates that the system is strapped to
the “topblock swap” mode.
The status of this strap is readable using the Top Swap bit
(Chipset Config Registers:Offset 3414h:bit 0).
NOTES:
1.
The internal pull-up is disabled after PLTRST#
deasserts.
2.
Software will not be able to clear the Top-Swap bit
until the system is rebooted without GNT3#/GPIO55
being pulled down.
Integrated 1.05 V VRMs is enabled when high
NOTE: This signal should always be pulled high
Datasheet
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