BD82HM55-SLGZS Datasheet, PDF (857/956 Pages) Intel Corporation – Intel® 5 Series Chipset and Intel® 3400 Series Chipset

Serial Peripheral Interface (SPI)
21.4.15
PREOP—Prefix Opcode Configuration Register
(GbE LAN Memory Mapped Configuration Registers)
Memory Address: MBARB + 94h
Default Value:
0000h
Attribute:
Size:
R/W
16 bits
Bit
15:8
7:0
Description
Prefix Opcode 1—R/W. Software programs an SPI opcode into this field that is
permitted to run as the first command in an atomic cycle sequence.
Prefix Opcode 0—R/W. Software programs an SPI opcode into this field that is
permitted to run as the first command in an atomic cycle sequence.
NOTE: This register is not writable when the SPI Configuration Lock-Down bit (MBARB + 00h:15)
is set.
21.4.16 OPTYPE—Opcode Type Configuration Register
(GbE LAN Memory Mapped Configuration Registers)
Memory Address: MBARB + 96h
Default Value:
0000h
Attribute:
Size:
R/W
16 bits
Entries in this register correspond to the entries in the Opcode Menu Configuration
register.
Note:
The definition below only provides write protection for opcodes that have addresses
associated with them. Therefore, any erase or write opcodes that do not use an address
should be avoided (for example, “Chip Erase” and “Auto-Address Increment Byte
Program”).
Bit
Description
15:14 Opcode Type 7—R/W. See the description for bits 1:0
13:12 Opcode Type 6—R/W. See the description for bits 1:0
11:10 Opcode Type 5—R/W. See the description for bits 1:0
9:8 Opcode Type 4—R/W. See the description for bits 1:0
7:6 Opcode Type 3—R/W. See the description for bits 1:0
5:4 Opcode Type 2—R/W. See the description for bits 1:0
3:2 Opcode Type 1—R/W. See the description for bits 1:0
Opcode Type 0—R/W. This field specifies information about the corresponding Opcode
0. This information allows the hardware to 1) know whether to use the address field
and 2) provide BIOS and Shared Flash protection capabilities. The encoding of the two
bits is:
1:0 _{00 = No address associated with this Opcode; Read cycle type}
01 = No address associated with this Opcode; Write cycle type
10 = Address required; Read cycle type
11 = Address required; Write cycle type
NOTE: This register is not writable when the SPI Configuration Lock-Down bit (MBARB + 00h:15)
is set.
Datasheet
857