BD82HM55-SLGZS Datasheet, PDF (123/956 Pages) Intel Corporation – Intel® 5 Series Chipset and Intel® 3400 Series Chipset

Functional Description
5 Functional Description
This chapter describes the functions and interfaces of the Intel^® 5 Series Chipset and
Intel^® 3400 Series Chipset.
5.1
DMI-to-PCI Bridge (D30:F0)
The DMI-to-PCI bridge resides in PCI Device 30, Function 0 on bus 0. This portion of
the PCH implements the buffering and control logic between PCI and Direct Media
Interface (DMI). The arbitration for the PCI bus is handled by this PCI device. The PCI
decoder in this device must decode the ranges for the DMI. All register contents are
lost when core well power is removed.
Direct Media Interface (DMI) is the chip-to-chip connection between the Processor and
the PCH. This high-speed interface integrates advanced priority-based servicing
allowing for concurrent traffic and true isochronous transfer capabilities. Base
functionality is completely software transparent permitting current and legacy software
to operate normally.
To provide for true isochronous transfers and configurable Quality of Service (QoS)
transactions, the PCH supports two virtual channels on DMI—VC0 and VC1. These two
channels provide a fixed arbitration scheme where VC1 is always the highest priority.
VC0 is the default conduit of traffic for DMI and is always enabled. VC1 must be
specifically enabled and configured at both ends of the DMI link (that is, the PCH and
processor).
Configuration registers for DMI, virtual channel support, and DMI active state power
management (ASPM) are in the RCRB space in the Chipset Config Registers
(Chapter 10.1.1).
DMI is also capable of operating in an Enterprise Southbridge Interface (ESI)
compatible mode. ESI is a chip-to-chip connection for server chipsets. In this ESI-
compatible mode, the DMI signals require AC coupling. A hardware strap is used to
configure DMI in ESI-compatible mode see Section 2.28 for details.
5.1.1
PCI Bus Interface
The PCH PCI interface supports PCI Local Bus Specification, Revision 2.3, at 33 MHz.
The PCH integrates a PCI arbiter that supports up to four external PCI bus masters in
addition to the internal PCH requests.
5.1.2
PCI Bridge As an Initiator
The bridge initiates cycles on the PCI bus when granted by the PCI arbiter. The bridge
generates the following cycle types:
Table 5-1.
PCI Bridge Initiator Cycle Types
Command
I/O Read/Write
Memory Read/Write
Configuration Read/Write
Special Cycles
C/BE#
2h/3h
6h/7h
Ah/Bh
1h
Notes
Non-posted
Writes are posted
Non-posted
Posted
Datasheet
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