BD82HM55-SLGZS Datasheet, PDF (879/956 Pages) Intel Corporation – Intel® 5 Series Chipset and Intel® 3400 Series Chipset

Thermal Sensor Registers (D31:F6)
22.2.21 AE—Alert Enable Register
Offset Address: TBARB+3Fh
Default Value: 00h
Attribute:
Size:
R/W
8 bit
Bit
Description
Lock Enable—R/W.
0 = Lock Disabled.
7
1 = Lock Enabled. This will lock this register (including this bit) and the following
registers: PPEC (offset 10h), CTA (offset 12h), and MGTA (offset 16h).
This bit is reset by a Host Partitioned Reset. Note that CF9 warm reset is a Host
Partitioned Reset.
Processor Core Alert Enable—R/W.
6
When this bit is set, it will assert the PCH’s TEMP_ALERT# pin if the processor core
temperature is outside the temperature limits.
This bit is lockable by bit 7 in this register.
Memory Controller/Graphics Alert Enable—R/W.
5
When this bit is set, it will assert the PCH’s TEMP_ALERT# pin if the Memory
Controller/graphics temperature is outside the temperature limits.
This bit is lockable by bit 7 in this register.
PCH Alert Enable—R/W.
4
When this bit is set, it will assert the PCH’s TEMP_ALERT# pin if the PCH temperature
is outside the temperature limits.
This bit is lockable by bit 7 in this register.
DIMM Alert Enable—R/W.
When this bit is set, it will assert the PCH’s TEMP_ALERT# pin if DIMM1-4 temperature
is outside of the temperature limits.
Note that the actual DIMMs that are read and used for the alert are enabled in the TRC
3
register (offset 1Ah).
This bit is lockable by bit 7 in this register.
NOTE: Same Upper and Lower limits for triggering TEMP_ALERT# are used for all
enabled DIMMs in the system.
2:0 Reserved
22.2.22
HTS—Host Status Register (Mobile Only)
Offset Address: TBARB+50h
Default Value: 000000000000h
Attribute:
Size:
R/W
48 bit
This register represents the data byte [19:14] provided to the external controller when
it does a read. Byte 14 is bit [7:0]. See Section 5.21.2.3 for more details.
Datasheet
879