BD82HM55-SLGZS Datasheet, PDF (456/956 Pages) Intel Corporation – Intel® 5 Series Chipset and Intel® 3400 Series Chipset

Gigabit LAN Configuration Registers
12.1.4
PCISTS—PCI Status Register
(Gigabit LAN—D25:F0)
Address Offset: 06h–07h
Default Value: 0010h
Attribute:
Size:
R/WC, RO
16 bits
Bit
15
14
13
12
11
10:9
8
7
6
5
4
3
2:0
Description
Detected Parity Error (DPE)—R/WC.
0 = No parity error detected.
1 = Set when the Gb LAN controller receives a command or data from the backbone
with a parity error. This is set even if PCIMD.PER (D25:F0, bit 6) is not set.
Signaled System Error (SSE)—R/WC.
0 = No system error signaled.
1 = Set when the Gb LAN controller signals a system error to the internal SERR# logic.
Received Master Abort (RMA)—R/WC.
0 = Root port has not received a completion with unsupported request status from the
backbone.
1 = Set when the GbE LAN controller receives a completion with unsupported request
status from the backbone.
Received Target Abort (RTA)—R/WC.
0 = Root port has not received a completion with completer abort from the backbone.
1 = Set when the Gb LAN controller receives a completion with completer abort from
the backbone.
Signaled Target Abort (STA)—R/WC.
0 = No target abort received.
1 = Set whenever the Gb LAN controller forwards a target abort received from the
downstream device onto the backbone.
DEVSEL# Timing Status (DEV_STS)—RO. Hardwired to ‘0’.
Master Data Parity Error Detected (DPED)—R/WC.
0 = No data parity error received.
1 = Set when the Gb LAN Controller receives a completion with a data parity error on
the backbone and PCIMD.PER (D25:F0, bit 6) is set.
Fast Back to Back Capable (FB2BC)—RO. Hardwired to ‘0’.
Reserved
66 MHz Capable—RO. Hardwired to 0.
Capabilities List—RO. Hardwired to 1. Indicates the presence of a capabilities list.
Interrupt Status^—RO. Indicates status of Hot-Plug and power management interrupts
on the root port that result in INTx# message generation.
0 = Interrupt is de-asserted.
1 = Interrupt is asserted.
This bit is not set if MSI is enabled. If MSI is not enabled, this bit is set regardless of the
state of PCICMD.Interrupt Disable bit (D25:F0:04h:bit 10).
Reserved
456
Datasheet