BD82HM55-SLGZS Datasheet, PDF (917/956 Pages) Intel Corporation – Intel® 5 Series Chipset and Intel® 3400 Series Chipset

Intel® Management Engine Interface (MEI) Subsystem Registers (D22:F0)
23.5.4
PCISTS—PCI Device Status Register (IDER—D22:F2)
Address Offset: 06–07h
Default Value: 00B0h
Attribute:
Size:
RO
16 bits
23.5.5
23.5.6
Bit
15:11
10:9
8:5
4
3
2:0
Description
Reserved
DEVSEL# Timing Status (DEVT)—RO. This bit controls the device select time for
the PT function's PCI interface.
Reserved
Capabilities List (CL)—RO. This bit indicates that there is a capabilities pointer
implemented in the device.
Interrupt Status (IS)—RO. This bit reflects the state of the interrupt in the
function. Setting of the Interrupt Disable bit to 1 has no affect on this bit. Only when
this bit is a 1 and ID bit is 0 is the INTc interrupt asserted to the Host.
Reserved
RID—Revision Identification Register (IDER—D22:F2)
Address Offset: 08h
Default Value: See bit description
Attribute:
Size:
RO
8 bits
Bit
Description
7:0
Revision ID—RO. See the Intel^® 5 Series Chipset and Intel^® 3400 Series Chipset
Specification Update for the value of the Device ID Register.
CC—Class Codes Register (IDER—D22:F2)
Address Offset: 09–0Bh
Default Value: 010185h
Attribute:
Size:
RO
24 bits
Bit
Description
23:16
15:8
7:0
Base Class Code (BCC)—RO This field indicates the base class code of the IDER
host controller device.
Sub Class Code (SCC)—RO This field indicates the sub class code of the IDER host
controller device.
Programming Interface (PI)—RO This field indicates the programming interface of
the IDER host controller device.
Datasheet
917