BD82HM55-SLGZS Datasheet, PDF (67/956 Pages) Intel Corporation – Intel® 5 Series Chipset and Intel® 3400 Series Chipset

Signal Description
Table 2-5.
Serial ATA Interface Signals (Sheet 3 of 3)
Name
Type
Description
SATA2GP /
GPIO36
SATA3GP /
GPIO37
SATA4GP /
GPIO16
SATA5GP /
GPIO49 /
TEMP_ALERT#
SATALED#
SCLOCK/
GPIO22
SLOAD/GPIO38
SDATAOUT0/
GPIO39
SDATAOUT1/
GPIO48
I
I
I
I
OD O
OD O
OD O
Serial ATA 2 General Purpose: This is an input pin which can be
configured as an interlock switch corresponding to SATA Port 2.
When used as an interlock switch status indication, this signal
should be driven to ‘0’ to indicate that the switch is closed and to ‘1’
to indicate that the switch is open.
This signal can instead be used as GPIO36.
Serial ATA 3 General Purpose: This is an input pin which can be
configured as an interlock switch corresponding to SATA Port 3.
When used as an interlock switch status indication, this signal
should be driven to ‘0’ to indicate that the switch is closed and to ‘1’
to indicate that the switch is open.
This signal can instead be used as GPIO37.
Serial ATA 4 General Purpose: This is an input pin which can be
configured as an interlock switch corresponding to SATA Port 4.
When used as an interlock switch status indication, this signal
should be driven to ‘0’ to indicate that the switch is closed and to ‘1’
to indicate that the switch is open.
This signal can instead be used as GPIO16.
Serial ATA 5 General Purpose: This is an input pin which can be
configured as an interlock switch corresponding to SATA Port 5.
When used as an interlock switch status indication, this signal
should be driven to ‘0’ to indicate that the switch is closed and to ‘1’
to indicate that the switch is open.
This signal can instead be used as GPIO49.
Serial ATA LED: This signal is an open-drain output pin driven
during SATA command activity. It is to be connected to external
circuitry that can provide the current to drive a platform LED. When
active, the LED is on. When tri-stated, the LED is off. An external
pull-up resistor to Vcc3_3 is required.
SGPIO Reference Clock: The SATA controller uses rising edges of
this clock to transmit serial data, and the target uses the falling
edge of this clock to latch data. The SCLOCK frequency supported is
32 kHz.
This signal can instead be used as a GPIO22.
SGPIO Load: The controller drives a ‘1’ at the rising edge of
SCLOCK to indicate either the start or end of a bit stream. A 4-bit
vendor specific pattern will be transmitted right after the signal
assertion.
This signal can instead be used as a GPIO38.
OD O
SGPIO Dataout: Driven by the controller to indicate the drive
status in the following sequence: drive 0, 1, 2, 3, 4, 5, 0, 1, 2...
These signals can instead be used as GPIOs.
Datasheet
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