BD82HM55-SLGZS Datasheet, PDF (671/956 Pages) Intel Corporation – Intel® 5 Series Chipset and Intel® 3400 Series Chipset

EHCI Controller Registers (D29:F0, D26:F0)
16.1.18
NXT_PTR1—Next Item Pointer #1 Register
(USB EHCI—D29:F0, D26:F0)
Address Offset: 51h
Default Value: 58h
Attribute:
Size:
R/W
8 bits
Bit
Description
Next Item Pointer 1 Value—R/W (special). This register defaults to 58h, which
indicates that the next capability registers begin at configuration offset 58h. This
register is writable when the WRT_RDONLY bit (D29:F0, D26:F0:80h, bit 0) is set. This
allows BIOS to effectively hide the Debug Port capability registers, if necessary. This
7:0 register should only be written during system initialization before the plug-and-play
software has enabled any master-initiated traffic. Only values of 58h (Debug Port and
FLR capabilities visible) and 98h (Debug Port invisible, next capability is FLR) are
expected to be programmed in this register.
NOTE: Register not reset by D3-to-D0 warm reset.
16.1.19
PWR_CAP—Power Management Capabilities Register
(USB EHCI—D29:F0, D26:F0)
Address Offset: 52h–53h
Default Value: C9C2h
Attribute:
Size:
R/W, RO
16 bits
Bit
Description
15:11
PME Support (PME_SUP)—R/W. This 5-bit field indicates the power states in which
the function may assert PME#. The PCH EHC does not support the D1 or D2 states. For
all other states, the PCH EHC is capable of generating PME#. Software should never
need to modify this field.
10
D2 Support (D2_SUP)—RO.
0 = D2 State is not supported
9
D1 Support (D1_SUP)—RO.
0 = D1 State is not supported
8:6
Auxiliary Current (AUX_CUR)—R/W. The PCH EHC reports 375 mA maximum
suspend well current required when in the D3_COLD state.
5
Device Specific Initialization (DSI)—RO. The PCH reports 0, indicating that no
device-specific initialization is required.
4 Reserved
3
PME Clock (PME_CLK)—RO. The PCH reports 0, indicating that no PCI clock is
required to generate PME#.
2:0
Version (VER)—RO. The PCH reports 010b, indicating that it complies with Revision
1.1 of the PCI Power Management Specification.
NOTES:
1.
Normally, this register is read-only to report capabilities to the power management
software. To report different power management capabilities, depending on the system in
which the PCH is used, bits 15:11 and 8:6 in this register are writable when the
WRT_RDONLY bit (D29:F0, D26:F0:80h, bit 0) is set. The value written to this register
does not affect the hardware other than changing the value returned during a read.
2.
Reset: core well, but not D3-to-D0 warm reset.
Datasheet
671