BD82HM55-SLGZS Datasheet, PDF (182/956 Pages) Intel Corporation – Intel® 5 Series Chipset and Intel® 3400 Series Chipset

Functional Description
5.13.8.1
PWRBTN# (Power Button)
The PCH PWRBTN# signal operates as a “Fixed Power Button” as described in the
Advanced Configuration and Power Interface, Version 2.0b. PWRBTN# signal has a 16
ms de-bounce on the input. The state transition descriptions are included in Table 5-29.
Note that the transitions start as soon as the PWRBTN# is pressed (but after the
debounce logic), and does not depend on when the Power Button is released.
Note:
During the time that the SLP_S4# signal is stretched for the minimum assertion width
(if enabled), the Power Button is not a wake event. See Power Button Override Function
section below for further detail.
Table 5-29. Transitions Due to Power Button
Present
State
Event
Transition/Action
S0/Cx
S1–S5
PWRBTN# goes low
PWRBTN# goes low
SMI or SCI generated
(depending on SCI_EN,
PWRBTN_EN and
GLB_SMI_EN)
Wake Event. Transitions to
S0 state
G3
PWRBTN# pressed
None
S0–S4
PWRBTN# held low
for at least 4
consecutive seconds
Unconditional transition to
S5 state
Comment
Software typically initiates a
Sleep state
Standard wakeup
No effect since no power
Not latched nor detected
No dependence on processor
(DMI Messages) or any other
subsystem
Power Button Override Function
If PWRBTN# is observed active for at least four consecutive seconds, the state machine
should unconditionally transition to the G2/S5 state, regardless of present state
(S0–S4), even if the PCH PWROK is not active. In this case, the transition to the G2/S5
state should not depend on any particular response from the processor (such as, a DMI
Messages), nor any similar dependency from any other subsystem.
The PWRBTN# status is readable to check if the button is currently being pressed or
has been released. The status is taken after the de-bounce, and is readable using the
PWRBTN_LVL bit.
Note:
The 4-second PWRBTN# assertion should only be used if a system lock-up has
occurred. The 4-second timer starts counting when the PCH is in a S0 state. If the
PWRBTN# signal is asserted and held active when the system is in a suspend state
(S1–S5), the assertion causes a wake event. Once the system has resumed to the S0
state, the 4-second timer starts.
Note:
During the time that the SLP_S4# signal is stretched for the minimum assertion width
(if enabled by D31:F0:A4h bit 3), the Power Button is not a wake event. As a result, it
is conceivable that the user will press and continue to hold the Power Button waiting for
the system to awake. Since a 4-second press of the Power Button is already defined as
an Unconditional Power down, the power button timer will be forced to inactive while
the power-cycle timer is in progress. Once the power-cycle timer has expired, the
Power Button awakes the system. Once the minimum SLP_S4# power cycle expires,
the Power Button must be pressed for another 4 to 5 seconds to create the Override
condition to S5.
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