BD82HM55-SLGZS Datasheet, PDF (192/956 Pages) Intel Corporation – Intel® 5 Series Chipset and Intel® 3400 Series Chipset

Functional Description
Table 5-35. Causes of Host and Global Resets (Sheet 2 of 2)
Trigger
Host Reset
without
Power Cycle¹
Host Reset
with Power
Cycle²
Global Reset
with Power
Cycle³
Straight to S5
(Host Stays
there)
Intel Management Engine Triggered Host Reset with
power down (host stays there)
No
Yes (Note 5)
No (Note 4)
PLTRST# Entry Time-out
No
No
Yes
S3/4/5 Entry Timeout
No
No
No
Yes
PROCPWRGD Stuck Low
No
No
Yes
Power Management Watchdog Timer
No
No
No
Yes
Intel Management Engine Hardware Uncorrectable Error
No
No
No
Yes
NOTES:
1.
The PCH drops this type of reset request if received while the system is in S3/S4/S5.
2.
PCH does not drop this type of reset request if received while system is in a software-
entered S3/S4/S5 state. However, the PCH will perform the reset without executing the
RESET_WARN protocol in these states.
3.
The PCH does not send warning message to processor, reset occurs without delay.
4.
Trigger will result in Global Reset with power cycle if the acknowledge message is not
received by the PCH.
5.
The PCH waits for enabled wake event to complete reset.
5.14
Note:
System Management (D31:F0)
The PCH provides various functions to make a system easier to manage and to lower
the Total Cost of Ownership (TCO) of the system. Features and functions can be
augmented using external A/D converters and GPIO, as well as an external
microcontroller.
The following features and functions are supported by the PCH:
• Processor present detection
— Detects if processor fails to fetch the first instruction after reset
• Various Error detection (such as ECC Errors) indicated by host controller
— Can generate SMI#, SCI, SERR, NMI, or TCO interrupt
• Intruder Detect input
— Can generate TCO interrupt or SMI# when the system cover is removed
— INTRUDER# allowed to go active in any power state, including G3
• Detection of bad BIOS Flash (FWH or Flash on SPI) programming
— Detects if data on first read is FFh (indicates that BIOS flash is not
programmed)
• Ability to hide a PCI device
— Allows software to hide a PCI device in terms of configuration space through
the use of a device hide register (See Section 10.1.65)
Voltage ID from the processor can be read using GPI signals.
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Datasheet